Original analysis of power integrity challenges shaping AI silicon, data center economics, and chip architecture.
The physics of transient voltage noise now determines what frequencies chips can sustain, what margins designers must hold, and what workloads data centers can run.
Read article →Building a complete board-to-transistor model of NVIDIA’s Hopper GPU in PDNLab, and what it reveals about the spatial distribution of voltage droop.
Read case study →Silent data corruption traces back to voltage droop. Traditional lumped models miss the physics. Here’s why Maxwell-accurate simulation changes everything for AI chip design.
Read article →A 158-grid power delivery model of the NVIDIA H100 exposes the voltage droop dynamics that define the electrical limits of modern AI accelerators — including a counter-intuitive result about workload sequencing.
Read analysis →The software running on a chip determines the electrical stress it experiences. Co-design means modeling the workload and the power grid together, before silicon exists.
Read article →