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Local Resonances in a Chip Power Grid

Constitution of On-chip Supply Noise

In a technology journal paper of a decade and a half ago, "Microprocessor Assembly Interconnect Pathfinding Challenges," I described a view of noise in a high-performance component as seen from a system (board, and packaging) perspective. The term 'Droop Theory,' first coined in this paper, covered the mathematics underlying the behavior of simple abstractions for the power delivery network (PDN). Lumped R, L, and C components in these equations helped arrive at gross estimations of on-chip noise. We were concerned then with the largest downward excursions of noise that we called 'Droops.' Droop theory sufficed to comprehend amplitude and frequency of such variations in power supply voltage provided to the chip. But that was looking in from the outside: we modeled the chip then as Cdie or, in essence, as a large capacitor!

Such abstract modeling, with lumped discrete components, may be of little help in studying on-chip noise. A chip power grid is often a continuous surface and is thus a voltage continuum. It is at times partitioned into global and local supply grids, where local grids power individual IP blocks. Grid architecture varies from chip to chip, IP block to IP block, and process to process. This makes modeling on-chip grids with lumped elements such as inductors, resistors, and capacitors rather cumbersome and computationally complex. The "RLCK" modeling approach bandied about in the industry is a hence a veritable Holy Grail.

Simulated noise in chip grids usually comes from decades-old IR Drop methodology, and is relative and approximate at best. I*R drop tools employ extracted resistance of innumerable power grid segments, ignore grid interconnect inductances, and claim that inductance is included through the addition of lumped package inductors. But this is again a 'system' level view of inductive elements, and therefore incapable of detecting, and optimizing, block power grid noise due to local inductance and temporal delays. In technical parlance, such an environment is not broadband: it loses high-frequency noise information. I discuss this to an extent in a recent Anasim PI-FP paper on Load Modulation and Continuum Noise Simulations.

Droop theory provides categories for noise components: i*r - resistive, L*di/dt - reactive, and ΔV=ΔI√L/C - resonant. I'd called it the 3R's of Interconnect when discussing that paper. But such classification is necessary only when dealing with circuits built from discrete elements. A continuum simulation environment integrates all these noise components into a single equation solved. This holistic formulation speeds simulations by orders of magnitude and provides true-physical noise results. In a continuum environment [1], noise is a superposition of the excitation of all possible responses of the PDN under the applied stimulus. The resistive, reactive, and resonant responses of droop theory are all manifested therein. Noise components are not calculated in discrete form, they blend with each other true-physically in amplitude and phase.

In the following example, we look at local power grid resonant noise in a full-system context through PI-FP continuum simulations. A measure of PI degradation often resorted to is maximum supply voltage excursion. Though this measure loses both spatial and temporal information, we use it to identify resonances. 3D dynamic views in PI-FP provide a backup method to inspect and verify our findings.

Experiment Setup

Figure 1 below shows a complete PDN from a supply through board and package pathways, and a chip power grid. Load blocks (charge consuming circuits) in purple, shown on the lowermost layer, connect to the chip power grid. They are distributed area loads, as it is in actual integrated circuits. Distributed capacitances, shown in parrot green on a layer above the load circuits, also connect to the chip power grid. Though illustrated separately, area capacitances may (and typically do) overlap with the distributed chip loads. For simplicity, and because I love to reuse old simulation models, only these few active and passive regions are included in this example.

Figure 1: Full PDN representation including chip/package power grids and board components.


Figure 2: On-chip dynamic voltage droops and PI hot spots with the full PDN stack.

A dynamic voltage droop (PI degradation) PI-FP simulation result of the PDN is shown in Figure 2. Results with added capacitance to minimize dynamic voltage drop in the evident PI hot spot (coordinates: 0,0) of the figure can be seen in this modified simulation that increased area capacitance C3 of Figure 1 above to 200pF.

Netlist and Stimulus

Figure 3 shows PDN physical and electrical aspects captured in netlist form in PI-FP. The statement "Cchip1 0.0 0.0 0.07 0.07 400e-12" defines an area capacitance, with its origin at (0.0 0.0) of grid chip1, of 400pF capacitance distributed in an area of 0.07 by 0.07 CM. The chip1 grid is defined by a "Gchip1 ..." statement included in the full simulation netlist, a portion of which is shown in the figure. Note that this capacitance, identified as C3 in the schematic, has been increased to 400pF in this experiment. The netlist snytax, stimulus input, and the continuum simulator are described in detail in the PI-FP Manual.

Figure 4 shows an example of a piecewise linear load current file. A half-sine current pulse of 100mA amplitude and 250ps pulse width approximates block supply current draw at clock edges. Supply current draw is maintained at zero for a time duration (gap) of 250ps, after which the load current profile is repeated as specified in the simulation netlist in "Ichip1 ..." statements. This particular load profile approximates a load spectral component of 2GHz with an amplitude of 100ma (maintained constant) in the experiment.

Figure 3: PDN Netlist in PI-FP


Figure 4: Single peak half-sine block load current (500ps period).


An interconnect description language capturing both physical and electrical aspects of power delivery network structures makes representing complex, 3-dimensional PDN's simple and intuitive. Multple stacked chips and 3D PDN's are otherwise modeled without physical information and with computationally complex nodal RLCK meshes. This is discussed to an extent in Power Integrity for Nanoscale Integrated Systems [2].

Simulations and Noise Measurement

A single load block current profile is varied only in frequency (by changing the load profile file) in a first set of simulation runs (Case 1). Load Block I2 of Figure 1 is chosen as the variable load, while both I1 and I3 remain loaded with an unchanging current profile. Peak noise amplitude measured is noted for each simulation run. Though this measurement loses spatial (location of peak droop on the grid) and temporal (time point in the 2ns total simulation run time) information, it helps detect gross amplification of noise due to local resonances suspected.

Based upon results of the first set of simulation runs, a second set (Case 2) varies load current profiles of two adjacent blocks, I1 and I3, to detect resonance combined with constructive interference. Load block I2 has an unchanged load profile for this set of simulation runs. Although it'd have been interesting to excite the grid with load block I2 at the resonant frequency detected in the first simulation run, this was not done in the current experiment.

Maximum noise results are plotted with frequency for both these simulation runs in Figure 5. Figure 6 illustrates spatial noise variation and droops, at resonance, in the second set of simulation runs.

Figure 5: Maximum chip noise with load frequency for two loading cases.


Figure 6: Power grid dynamic noise view at resonance (case 2).


Discussion: Local Resonance, Noise Peaking, and Constructive Addition

The relative constancy of the largest dynamic voltage droop (DVD) in the first third of the frequency range is notable in Figure 5 above. Both Case 1 and Case 2 show peak noise holding steady until about 2.5 GHz. This appears to lend some credence to the use of peak noise value as a measure of chip PI degradation.

For Case 1, with only load I2 varied in frequency, one may argue that peak noise may not occur near this load block. Besides, capacitance C2 is 500pF, the largest area capacitance in this experiment. Yet, as load frequency content increases beyond 2.5 GHz, noise increases from the baseline value of 36mV up to a peak of ~44mV at 6.25 GHz. The spectral content of load current has a significant impact on chip noise, of as much as 20%. Since grid excitation is local, this increase in noise most likely occurs near I2 in Case 1. This is readily verified with a visibly dynamic, spatiotemporal view of noise in PI-FP as in Figure 2. Frequency specificity is also confirmed by the fall of chip noise beyond the frequency of maximum noise.

Case 2 is rather more interesting. Chip grid noise remains at a baseline value of 41mV (likely developed by I2) until about 3 GHz. It then rises to a peak of ~49mV at 5 GHz, falls as frequency increases, peaks again at 7.5GHz to ~46mV, and falls further. Again, noise increases by as much as 20% at a specific frequency, while also peaking at another frequency further ahead. Recall that two load blocks, I1, and I3, excite the chip grid with the same varied stimulus in this case. And that these load blocks associate with capacitances of values of 300pF and 400pF respectively. Hence, the dual peaks of noise, in this case, point to varied resonant frequencies in this region.

But - I2 neighbors an area capacitance of 500pF. I3 connects to the chip grid near C3 of value 400pF. Why then is the first resonant frequency seen in Case 2 less than that of Case 1? Here's where physical aspects of the load blocks and capacitances come into play. I2 has a higher current density (smaller block area) and is closer to C2, with correspondingly reduced response delay to charge demand. I3, though near lesser capacitance C3, encounters more time delays as compared with I2. Its resonant interaction with C3 thus occurs at a lower frequency.

A more careful experiment may measure noise at nodes of the chip grid where the applied load stimulus changes. This may demonstrate a noise variation with frequency, and amplitude range, more typical of resonant phenomena.

Figure 6 is a snapshot of chip DVD at resonance in Case 2. See the peak DVD of ~49mV near I3? Propagation of noise from regions of stimulus (I1, I3) into each other is evident. This is also seen in dynamic form in Figure 2. Is it fair to say that noise on a grid isn't just I*R Drop, but a complex, often nonlinear or chaotic, combination?


1) Yes, chip grids demonstrate local resonances! Some theoretical aspects of such phenomena are reviewed in [2].
2) Peak noise does not correlate with Peak-I when frequency, and reactive and resonant noise matter.
3) Local resonant noise can significantly increase chip DVD...by ~20% as measured in this experiment.
4) Such resonant noise principally depends upon circuit activity, distributed loads and caps, and on-chip delays.
5) A continuum simulation environment enables holistic, and spatiotemporal, DVD noise exploration.
6) A true physical analysis capability permits exploration of advanced PI degradation phenomena such as local resonances and constructive noise interference. More in [1] and [2].

This experiment was created and run in PI-FP in its command-line mode. For more on PI-FP, or such experiments, please contact us.


[1] Raj Nair and Donald Bennett, Anasim Corp. "Power Integrity Analysis and Management for Integrated Circuits," Pearson Education - Prentice Hall, 2010.
[2] Masanori Hashimoto and Raj Nair, "Power Integrity for Nanoscale Integrated Systems," McGraw Hill, 2014.
[3] Raj Nair, Anasim Corp. "IC Floorplanning and Power Integrity," SOCcentral 2010.
[4] Raj Nair and Donald Bennett, Anasim Corp. "Dynamic Voltage Droops and Total Power Integrity," EETimes May 2008.

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