What is PI-FP?
A graphical introduction is provided in these two slides (use buttons at the top of the slides page for navigation) also downloadable as a high resolution PPT.
PI-FP stands for power integrity aware floor planning. But it is a lot more than that: it is a true physical power delivery network simulator, a system-down-to-IP-block-level power integrity evaluation environment, a design methodology that brings PI awareness to the front end of the design process,
and a chip/IP Block physical design (metal and capacitance resources) and floor plan optimizer. Its principal role is to provide designers with detailed insight into the spatiotemporal and dynamic nature of power integrity degradation.
Overview of the PI-FP simulation environment.
At its core, PI-FP implements a simple, spice-like, true-physical description language for all key power delivery network (PDN) components.
Simple statements (PI-FP Manual) describe power grids, transmission lines, distributed area capacitances, area current loads, and lumped capacitors. PI-FP implements high level abstraction
that also captures physical and electrical aspects of PDN components. For instance, an on-chip power grid is represented as a 2-dimensional grid with
R, L, and C values. Circuit blocks are represented by both their distributed capacitance and their distributed current consumption. Transmission lines are represented
in the same manner as power grids.
The interaction of these physical components is determined in an electromagnetic field-solver that employs Anasim's proprietary
Effective Current Density (ECD) algorithm . This unique combination provides true-to-physics simulation results with greatly reduced computational burden.
In other words, you get to see dynamic voltage droops, as they truly happen, in minutes!
A decade-old, low resolution, minutes-long and regrettably silent, FLASH animation on PDN description netlists and simulation can be viewed in a separate window in this
ESL in this demonstration stands for 'Electronic Systems Level,' and POWERESL is an intermediate stage of PI-FP development.
What are TRUE-PHYSICAL Results?
Noise propagating through a capacitance array in a chip grid (RLCSIM).
The above figure illustrates noise propagation in a uniform 7mm by 5mm chip grid. Noise generated by a source radiates in all directions and, in accordance
with EM wave propagation in the given substrate and interconnect, arrives at a curiously shaped capacitance array. What happens to the noise wave as
it passes through the region occupied by the capacitance array? Did this capacitance array "shield" circuits behind it from noise, as often claimed?
Mind that EM wave delay is proportional to the effective √LC encountered,
and that EM waves are much the same as light.
A key advantage is the ability to capture an entire PDN model, from a circuit board with dimensions in centimeters down to IP blocks with dimensions in micrometers, and simulate it in minutes.
GUI's enhance this capability, and have evolved over the years.
This rapid turnaround makes the PI-FP analysis environment eminently suitable for front-end 'What-If' design exploration.
Including true-physical accuracy, the PI-FP methodology facilitates early validation of design choices and first-time-correct implementations.
In the following sections, we look at various graphical user interfaces engaging with capabilities and
applications of PI-FP.
Active Noise Regulation and Simulated Results
Figures 1 and 2 below show the earliest example of a system-level simulation using PI-FP.
An Active Noise Regulator (ANR), patented by ComLSI as a PI innovation, is shown reducing on-chip supply droop by ~40%.
Simulations were carried out with PDN description written out in netlist form in this example. GNUPLOT and
animation capture in GIF file form enabled data visualization. Theoretical aspects of ANR concepts are discussed
in Anasim's second book on power integrity .
Figure 1: ANR devices mounted on an SoC Package (patented).
Figure 2: Simulation results of supply voltage change delta (Vdd-Vss).
IP Block Power Integrity Analyses
IP block level design explorations for power integrity are easy in PI-FP. Figures 3 and 4 below illustrate load current modulation and corresponding PI impact.
Recall that input to PI-FP includes stimulus in the form of load current waveforms. Figure 3 illustrates load current shaping.
Power integrity degradation on a block grid within a larger chip/package context (a true-physical operating environment) is shown in Figure 4.
Read more on this experiment exploring load wave shaping and dynamic voltage drop.
Figure 3: Block load current shaping in PI-FP's GUI.
Figure 4: Grid noise with a single peak block load current.
Full-Chip Block Placement and Decoupling
The next example illustrates block noise propagation and interactions in a full-chip context. The entire PDN extending from IP blocks through the global chip grid,
package power grid, and board power pathways is represented. Lumped non-ideal capacitors on the package and board are readily represented by arrays of
transmission lines that manifest spectral impedance variation better than simple R, L, C models (discussed ahead). A requirement
for additional decoupling in a corner of the chip is evident from the simulation.
Figure 5: Full PDN representation including chip/package power grids and board components.
Figure 6: On-chip dynamic voltage droops and PI hot spots with the full PDN stack.
Results with added capacitance to minimize dynamic voltage drop in the evident PI hot spot of Figure 6 above can be
seen in this modified simulation result
that increased area capacitance C3 of Figure 5 above by 200pF.
Advanced Investigations: System Resonances and Local Grid Impedance
It is common to talk of PDN impedance when discussing power integrity. Impedance peaks, when excited by spectral components
of chip load, often result in resonant noise. This phenomenon occurs at the system level all the way down to IP blocks in a typical
high-performance System-on-Chip (SoC). Yes, it is not just boards that encounter supply ringing, but packages and chips too. PI-FP's
true-physical environment facilitates both time-domain (resonant noise) and frequency-domain (impedance, and its variation)
investigations through the entire PDN stack.
Figure 7: Example PDN stack (Chip-package-board) abstraction and system resonance droop.
(See more zoomed-in views of the above example in high resolution.)
Figure 8: Node noise in a chip/pkg power grid with a 400mA, 500MHz sinusoidal load current.
As in Figure 7 above, PI-FP determines dynamic voltage drop (droop to be exact) in any node or sub-area of a surface (chip grid, pakage grid)
and saves it in simple ASCII form for visualization or further computation. It is thus a simple matter to obtain the responses of any node to varied
spectral components of load. A 400mA, 500MHz load current excitation (2ns sinusoidal period) produces ~20mV noise on a node in a chip grid in
Figure 8 below. Figure 9 shows this response increasing to ~30mV with the same load current at a frequency of 1 GHz (1ns period). A simulation script,
or BATCH file, that sweeps load currents through desired frequencies, can readily provide PDN impedance variation with frequency. PI-FP's simulation
speed combined with today's mult-core processors makes this exercise speedy and real-time.
Figure 9: Node noise in a chip/pkg power grid with a 400mA, 1GHz sinusoidal load current.
Most experiments above, created and run in PI-FP, took minutes for design capture and simulation.
A true-physical 'what-if' analysis environment greatly enhances early design exploration. For more on PI-FP, or such experiments, please contact us.
A language for true-physical, CONTINUUM, abstractions for the entire PDN component stack
A NEW ALGORITHM for an EM FIELD SOLVER for PDN simulations
A FAST Grid & T-Line simulation engine for spatiotemporal and dynamic voltage drop
A METHODOLOGY for PI awareness at the front-end of the design process for early, 'what-if' analyses
A TRUE PHYSICAL simulation environment including TIME and FREQUENCY DOMAIN analyses
Authored Books on Power Integrity