PDNLab™ — Shift-Left Power Planning on Maxwell-Accurate PDN Models

PDNLab 4D voltage continuum surface — dynamic voltage droop propagating across a chip power grid over time

The 4D Continuum

Droop as an electromagnetic continuum

An on-chip power grid is not a single supply node. It is a vast, distributed mesh of metal — with resistance, inductance, and capacitance at every point — feeding billions of transistors. At the speed AI silicon switches, a current change in one region cannot update the whole grid at once: the disturbance has to travel, propagating outward as a wave, governed by the same distributed physics that describes any electromagnetic medium.

So the supply voltage isn't a number — it's a field spread across the die. PDNLab treats it that way: because every R, L, C, and current term carries an explicit spatial coordinate, its native output is a four-dimensional field — voltage as a function of (x, y, layer, t) across the entire network.

Watch a wavefront launch from a switching cluster, propagate across the grid, reflect at the bump array, and converge with other cores' waves. Cumulative voltage droop is, by definition, a spatiotemporal phenomenon — PDNLab shows it as one — the difference between a scalar sign-off number and an actionable, spatial answer a designer can act on at RTL.

Why the on-chip power grid behaves as an electromagnetic surface

The Abstraction

Abstraction to overcome PI compute complexity

Conventional power-integrity tools represent the chip as polygons — millions of metal shapes fed into a finite-element-style solver. At nanoscale, that complexity “explodes exponentially and hits a wall,” so polygon-based tools retreat to the one thing they can still afford: static IR-drop.

PDNLab's engine takes the opposite path. It exploits the differential, symmetric, and periodic nature of every power grid: differential Vdd/Vss bus pairs become transmission planes, so a single charge-and-voltage equation replaces a long bus — or an entire 3-D grid — of countless polygons.

A patent-pending Effective Current Density (ECD) method then fuses the whole grid into one continuous surface, so the grid's construction no longer drives analysis cost. Current draw and decoupling are distributed across area, exactly as they are in silicon.

The payoff: a true-dynamic view of I·R + L·di/dt + C·dv/dt across the full board-to-die stack — an order of magnitude (≈10×) faster than conventional analysis. Fast enough for rapid “what-if” exploration at the floorplan stage.

Distributed, not lumped

Enhances static I·R drop with distributed I·R, L·di/dt, and C·dv/dt — the components that actually dominate dynamic droop.

Continuum, not polygons

The ECD surface removes grid construction from the analysis cost — so model size scales with the design, not with polygon count.

Reveals resonances

Surfaces 2-D grid and system resonances, noise propagation, and interference — phenomena a scalar IR-drop number can never show.

Modeling with PDNLab

From functional blocks to the full stack — die, package & board

PDNLab models the complete power-delivery path — not as separate hand-offs, but as a single distributed, three-dimensional electromagnetic structure.

Distributed power grids — on-die metal layers as sheets with sheet resistance, inductance per length, and capacitance per area from the real stack.
Per-block current sources — each functional block drives its own current profile at its own location and time.
Transmission lines, vias, bumps & solder balls — full propagation through package and board, captured physically.
Decoupling capacitance — ideal and physical decap placed spatially across the design.

The questions it answers: where droop concentrates, how it propagates board-to-die, which workload sequences create the worst cumulative droop — and the lowest supply voltage the design can safely run at.

PI-Aware Design

PI-aware design for better engineering

For decades, power-integrity sign-off has lived at the end of the design flow — after place-and-route, when the floorplan and metal stack are frozen and a problem is most expensive to fix.

By then, a dynamic voltage droop violation means a late-stage ECO scramble — or, worse, a silicon respin discovered in the lab. The information that could have prevented it existed at the architecture stage; the tools to act on it did not.

PDNLab closes that gap. It brings full-stack droop analysis to the architecture and RTL phase, where the floorplan is still fluid and power delivery can shape the design instead of merely auditing it.

Shift left. Identify IR-drop and dynamic-droop hotspots while you can still move a block, resize the grid, or place decoupling — not after the design is committed to metal.

Why It Matters

The cost of finding droop late

Every voltage-droop problem caught after place-and-route is exponentially more expensive than one caught at RTL. Shifting left collapses three of the most painful costs in a tapeout.

Fewer ECOs

Reduce late-stage ECO cycles

Fixing a droop hotspot after routing means costly engineering change orders, re-routing, and re-verification. Catch it at RTL and the fix is a floorplan decision, not a scramble.

No respins

Eliminate silicon respins

A droop that escapes to silicon is a multi-month, multi-million respin found in the lab. Early full-stack analysis removes the class of failure before metal is committed.

Faster TTM

Accelerate time-to-market

Every avoided ECO and respin is schedule reclaimed. Power-aware decisions made early keep the design converging instead of looping back.

FAQ

Questions, answered

Why hasn't the industry adopted this tool already?

Because the approach is genuinely different — and for most of the industry's history it didn't have to be. Conventional flows are built around late-stage, polygon-based, static IR-drop sign-off. When a static check “passed,” teams simply over-designed the grid and padded voltage margin to cover the dynamic effects they couldn't see. That worked while supplies were high and currents were modest.

The physics that PDNLab captures — distributed L·di/dt, wave propagation, resonance, constructive interference — was pioneered by Anasim (as PI-FP) back in 2006–2008, ahead of the era that made it unavoidable. At today's ~0.6 V rails and thousands of amps with enormous di/dt, you can no longer guardband your way out, and silent data corruption at fleet scale has made dynamic droop a board-level concern. The need has finally caught up with the method.

PDNLab is the modern, productized realization of that approach — and it's designed to complement existing Synopsys, Cadence, and Siemens flows, not rip-and-replace them, so adoption is a methodology shift, not a tool migration.

Does PDNLab replace my sign-off tools?

No. PDNLab adds the early, dynamic, spatial view that traditional sign-off flows lack — it sits at the architecture and floorplan stage and feeds better decisions into the flow you already use. Your final-stage sign-off tools still do their job; PDNLab simply means they find far fewer surprises.

How is it roughly 10× faster than conventional analysis?

It doesn't model the grid as polygons. Differential power-bus pairs are represented as transmission planes, and the patent-pending Effective Current Density (ECD) method fuses the entire grid into one continuous surface. The grid's construction stops driving the analysis cost — so a full board-to-die transient runs an order of magnitude faster than a finite-element / polygon-based equivalent.

How early in the flow can I use it?

At the architecture, RTL, and floorplan stage — before placement and routing begin, while the floorplan is still movable. That's the whole point: catch IR-drop and dynamic-droop hotspots when fixing them is a design decision, not a respin.

What do I provide — and how do I get current profiles at RTL?

Two things: your floorplan blocks (location and area) and a current profile — I(t), amps vs. time — per block, since PDNLab models distributed current sources. The natural question is where I(t) comes from before you have final layout. You already generate the data:

From RTL power analysis (the standard path). Simulate the RTL against representative workload stimulus to capture switching activity (VCD / FSDB / SAIF), then run it through the RTL/gate power tools you already use — Ansys PowerArtist, Synopsys PrimePower, or Cadence Joules. They produce a time-resolved power waveform per block; convert with I(t) = P(t) / V_dd. That per-block waveform is exactly the PDNLab current source.

From a power budget (earliest, pre-RTL). Derive each block's mean current from its area and TDP, then attach a block-type pulse shape matched to its activity — broadband vs. narrowband, hard vs. soft edges — integrated to the charge budget. PDNLab takes those directly.

Either way there's no new characterization burden — PDNLab reuses the activity data your flow already produces.

Can PDNLab help me find V_min and reduce voltage margins?

Yes — and it's one of the highest-value reasons to use it. When you can't see real dynamic droop, you guardband: you raise the supply margin to cover the worst case you can't quantify. But that margin is expensive. At a 0.6 V rail, a 30 mV guardband is 5% of the entire operating range, and every unnecessary millivolt is performance and efficiency left on the table.

Because active power scales ∝ V² and leakage ∝ exp(V), safely lowering the operating voltage has an outsized payoff. By giving you the true spatiotemporal droop — where and when the supply actually sags under your workloads — PDNLab lets you “bring the roof down”: find the real V_min, shrink the margin with confidence, and arrive at the lowest-power, lowest-energy design without risking timing or first-silicon success.

What does it compute that an IR-drop tool misses?

Distributed L·di/dt and C·dv/dt, wave propagation across the grid at finite velocity, package–chip resonance, and constructive interference (“rogue waves”). It even shows the counter-intuitive cases — where added decoupling capacitance can amplify noise by focusing a wavefront, not just suppress it. A scalar IR number can't represent any of that.

Can it handle modern GPUs, chiplets, and wafer-scale designs?

Yes. Anasim has built a full-stack PDNLab model of the NVIDIA® H100 — 158 power grids, 175 current sources, 794 transmission lines, 1,500+ nodes. Because complexity isn't tied to polygon count, the continuum approach scales to large, multi-die, and even wafer-scale power-delivery problems where lumped models break down entirely.