Why AI Cores Need to Be Modeled with PDNLab

An AI core has no single droop. Its droop surface is the convolution of the physical power grid with a specific workload's spatiotemporal current, and it changes with every workload the core executes. A worst-case scalar cannot represent it, and a single synthetic stimulus cannot locate its worst case. This article sets out why workload structure and physical layout jointly determine the droop surface, and why each workload of interest must be modeled against the physical grid — the analysis PDNLab is built to perform.

The droop surface as a transfer function

An AI core's droop surface is a response, not a fixed property of the chip. The grid's spatial impedance — set by the floorplan and the metal stack — is convolved with the workload's current distribution over time: Droop(x, y, t) = Z_grid(x, y) ⊛ I_workload(x, y, t).

Both terms are required. The grid alone is inert; the current schedule alone is a table of numbers. The droop is the interaction of the two. Because the current term changes from one kernel to the next, a single core exhibits a family of droop surfaces — one per workload. There is no single "droop of the core" to characterize or sign off, and any method that produces one has discarded the information that matters.

Why AI cores violate conventional PI assumptions

Conventional power-integrity analysis assumes switching activity is statistically decorrelated, spatially averaged, and bounded by a worst-case toggle rate. AI cores satisfy none of these conditions.

Spatial coherence. A systolic or tensor array is a regular field of identical processing elements switching in lockstep. Their current is correlated across large contiguous areas, with no statistical cancellation. On an H100 streaming multiprocessor, a warpgroup matrix-multiply burst draws approximately 4 A concentrated in about 18% of the SM area, repeated twice within a 5 ns window.

Temporal coherence. Tensor cores switch on the clock edge, so their di/dt is coherent and does not average across a distribution of arrival times.

Structural regularity. A geometrically regular array driven by a periodic clock is the canonical configuration for standing waves and resonance.

Data dependence. Sparsity, numeric precision, and operand values modulate the current, so a given kernel produces a distribution of current signatures rather than a fixed waveform.

Consequently, vectorless and statistical IR-drop methods are unsound for AI cores. They overestimate droop in benign regions and underestimate it in precisely the coherent, resonant cases that govern reliability. Silent data corruption is the downstream symptom; the mechanism is the subject here.

Workload structure shapes the droop surface

Treating the droop surface as a response makes its determinants explicit. Several are software decisions with no effect on the computed result. Scheduling and training-loop periodicity, which drive spatial droop and resonance, are treated in our analysis of how kernel execution creates voltage emergencies. The following workload parameters reshape the surface directly:

• Dataflow direction determines the direction of droop propagation. Weight-stationary and output-stationary schedules stream activations along different axes; the active wavefront, and the droop trough tracking it, propagates accordingly.
• Tiling and dispatch determine which elements are active and when. The compiler's blocking of a GEMM across the array fixes the spatiotemporal current map.
• Operator fusion determines plateau-versus-burst behavior. Fused kernels sustain current continuously; unfused kernels insert relaxation gaps and high-di/dt steps between launches.
• Numeric precision determines current density. Moving from FP16 to FP8 to INT8 increases multiply-accumulates per unit area per cycle, raising current density and di/dt in the same footprint.
• Batch size and sequence length determine spectral content. They set burst durations and repetition rates, shifting the workload's frequency content relative to the package resonances — approximately 50 to 500 MHz at the die-to-package interface and 1 to 50 MHz at the package-to-board interface.

Physical layout shapes the droop surface

The floorplan is the second term in the convolution and an equally strong determinant of the result.

• Distance to the power-bump array. Droop at a tensor cluster scales with its distance from the C4 bumps feeding it. The floorplan fixes each workload's electrical center of gravity relative to the bump map.
• Array boundaries. The array's extent sets the reflection geometry for voltage waves, and its size relative to wave velocity sets the resonant frequency. Corner-to-corner propagation across a large die is 10 to 50 ns — long enough for activation timing and geometry to interfere.
• On-die SRAM. Memory banks act simultaneously as local decoupling capacitance and as current loads. Their placement relative to the compute array determines how the array is fed during a burst.
• Grid anisotropy. A power grid presents different resistance and inductance along versus across its metal direction. A dataflow aligned with the high-inductance axis droops differently from one oriented across it.
• Convergence zones. The locations where wavefronts from adjacent cores meet — the sites most exposed to the constructive interference described in our analysis of rogue waves — are determined by layout, not by chance.

The case for per-workload modeling

The worst case for an AI core is not its highest-power workload. It is the workload whose spatial and spectral structure coincides with the grid's vulnerabilities. That workload cannot be identified by inspection or by a flat worst-case stimulus; it must be found by simulating realistic workloads against the physical grid.

Characterization is therefore a set of droop surfaces — training GEMM, inference decode, attention, and the specific layer, precision, and batch configuration that produces the deepest droop — not a single number. From that set, V_min can be set per workload or operating mode rather than as one global guardband, recovering margin and power. Because new models are new stimuli, a physical grid model also supports evaluating future workloads against existing silicon before tapeout.

The power grid as an electromagnetic medium

The on-chip power grid is a distributed electromagnetic medium across which voltage propagates as waves, not a lumped supply node. AI workloads are the most demanding stimulus this medium encounters: the most spatially coherent, the most periodic, and the highest in di/dt. Determining the electrical conditions at the transistors requires exciting the physical grid with the actual workload current and observing the resulting field. The droop surface is that result, and it differs by workload because each workload excites the medium differently.

Design decisions enabled by per-workload droop surfaces

A per-workload droop surface supports decisions a scalar margin cannot:

• Floorplanning. Locate high-di/dt clusters near bumps, orient arrays with respect to grid anisotropy, and place decoupling capacitance where the dominant workloads draw current.
• Scheduling and tiling. Select dispatch patterns that decorrelate current — round-robin distribution, staggered activation — converting a compiler decision into measurable droop reduction.
• Voltage. Set guardband and adaptive voltage per operating mode rather than to a single global worst case.
• Verification. Run a workload stress suite before tapeout to identify the resonant, rogue-wave workload, not only the highest-power one.

Modeling requirements, and why PDNLab

This analysis requires a model with two properties: per-block current sources that each carry an explicit (x, y) coordinate, and a continuum representation of the grid. Together they allow a workload's time-resolved current to drive the physical grid and produce the corresponding droop surface, as described in our walkthrough of modeling an AI accelerator core. The ECD engine's order-of-magnitude speed advantage makes evaluating a library of workloads practical rather than exceptional.

An AI core is not a single electrical object with one droop to sign off. It presents a distinct electrical environment for each workload it executes, and the critical case is frequently not the obvious one. Modeling the core in PDNLab — driving the physical, distributed grid with realistic, spatially resolved workload current — exposes those environments at the floorplan stage, while the design can still be changed.