A modern superchip is built by hundreds of engineers across many disciplines — but whether its power supply holds steady under load is decided early, by a handful of questions asked by one often-overlooked person. Call them the PDN architect: the experienced power-delivery engineer who dictates how current reaches every transistor, and who, long before the first piece of metal is drawn, asks the questions that determine whether the chip will compute correctly at all. This is a look at that role from inside a chip program.
How a superchip begins
A new program starts from some mix of a roadmap slot, a workload shift, competitive pressure, or a customer commitment. Executives, a chief architect, and the product team set the top-level targets — and a few of those targets quietly decide the chip’s entire power-integrity fate before any design work happens:
- TDP and supply voltage. These are the peak current. 700 W at ~0.8 V is on the order of 900 A. The very first power-delivery question — “can we physically move this many amps onto the die?” — is answerable at this moment.
- Process node — which fixes sheet resistance, density, and what on-chip capacitance is available.
- Packaging strategy — monolithic or chiplet, 2.5D/3D, how many HBM stacks. This decides whether the power network is a die on a package or a coupled, multi-die system.
- Voltage domains and how aggressive the DVFS / adaptive-voltage scheme will be — which trades efficiency against transient noise.
The best programs have a senior PDN architect in this room. The weaker ones discover that power delivery is a problem eighteen months later.
The team around them
A superchip is a multi-year effort spanning hundreds of engineers and several sites. The groups that touch power delivery:
| Team | Role in power delivery |
|---|---|
| Chief architect | Owns the whole chip; arbitrates power vs. performance vs. area vs. cost. |
| Microarchitecture / RTL | Compute tiles, memory, IO, interconnect — the teams that create the current demand. |
| Physical design | Floorplan and place-and-route; implements the grid the architect specifies. |
| PDN / power-integrity team | Owns the network: grid topology, decap, bump map, voltage domains. Where the PDN architect lives. |
| Advanced packaging | Substrate, interposer, HBM integration, bump map — co-owns the package PDN. |
| Board / system power | VRM/PMIC, telemetry, board planes. |
| Thermal | Tightly coupled to power and, increasingly, to power integrity. |
| Signoff / methodology | Owns the tools and flows everyone runs. |
| Post-silicon / characterization | Measures the real chip and closes the loop back to the next one. |
The PDN architect is usually not the head of any one of these. They are a cross-cutting senior engineer — often a principal or distinguished engineer — whose authority is informal but decisive, and who sits across the program from definition through sign-off.
The leverage problem
Here is the structural tension that defines the role. Power-integrity decisions have their greatest leverage early — at architecture and floorplan, where the grid topology, decap strategy, bump map, and block placement are still movable. But most of the PI effort in a typical flow happens late, at sign-off, after place-and-route, when the floorplan and metal stack are frozen and the only remaining lever is adding decoupling capacitance.
| Phase | Power-integrity reality |
|---|---|
| Definition | Targets set the current, package, and domains — the cheapest place to fix anything, if anyone is asking. |
| Architecture / floorplan | The shift-left window: grid, decap, and placement are all still movable. |
| Implementation | Grid built, decap inserted; iterative analysis as the design firms up. |
| Sign-off / tapeout | Static IR, dynamic droop, EM; most PI effort lands here — with the least room to act. |
| Post-silicon | Measure real droop; reclaim margin with firmware (AVS, droop detectors). |
The PDN architect’s entire value is in fighting that gravity — in moving the decisions forward, into the window where they are cheap, against a flow that wants to defer them.
What the PDN architect actually does
It is tempting to imagine the role as “the person who runs the IR-drop tool.” It is almost the opposite. The real work is three things, and none of them is pushing a button:
- Setting the strategy early. The grid topology, the decap budget and — crucially — where it goes, the bump map, the voltage-domain partition, the supply noise budget. These are architecture decisions, made before implementation, that the rest of the program inherits.
- Owning the worst case. Deciding what the chip must actually survive — the synchronized “power virus,” the realistic AI workload current profile, the case where a workload’s power spectrum lands on a PDN resonance. Much of power integrity is the argument over what the worst case truly is.
- Asking the right questions in the architecture room. Translating “this floorplan” into “this will droop here” while it is still cheap to move a block, widen a grid, or relocate a reservoir of charge.
The right questions
A PDN architect earns their keep precisely because they ask these early, when the answers can still change the design:
At definition:
- What is the peak current (TDP / Vdd), and can the package and bumps physically deliver it?
- Monolithic or chiplet? How many HBM stacks, and do they share the logic power network?
- How many voltage domains, and how aggressive is the DVFS / AVS scheme — given that aggression buys efficiency but worsens di/dt?
At architecture and floorplan — the highest-value questions:
- Where are the hottest blocks, and how synchronized do they switch? (di/dt, not just average power.)
- Do hot aggressors sit next to sensitive victims — SRAM, an analog PLL?
- What is the decap budget per region, and is there whitespace to place it where the fast events are, not just wherever it fits?
- What grid density and metal allocation, and what on-die impedance does that produce?
- What are the PDN resonant frequencies, and do they overlap the workload’s power spectrum?
- How does charge actually reach this block — bump density, loop inductance, the “last inch”?
- What is the Vmin noise budget, and how much guardband are we giving away to uncertainty? (Every millivolt is performance left on the table.)
- How will board, package, and die interact — where are the multi-droop impedance peaks? For chiplets, how does one die’s transient couple into its neighbor, and how does HBM reach the logic rail?
At sign-off:
- Does full-stack, board-to-die dynamic analysis show droop within budget for the worst realistic workload — not just a static IR pass?
- Are we trusting tools that structurally miss L·di/dt?
- What is the post-silicon safety net — droop detectors, adaptive clocking, AVS — and how much margin does it let us reclaim?
The pattern. Notice that almost none of these are tool outputs. They are judgments — about workloads, placement, and risk — that a tool can inform but not make. That judgment, asked early, is the entire job.
The scarce graybeard
The person who really dictates power distribution is usually someone who has personally been burned by a droop bug on a previous chip — who has seen silicon throttle, or fail intermittently, or miss its frequency target because a margin they didn’t take turned into a droop they didn’t predict. That scar tissue is the qualification. It is also why the role is scarce: the questions above are obvious only in hindsight, and the engineers who hold them in foresight are few, senior, and spread thin.
This is why the power-integrity wall is, at bottom, an expertise problem as much as a physics one. The physics has been understood for two decades. What has lagged is the ability to put that expertise into every design room, early, with an instrument fast and accurate enough to answer the floorplan-stage questions before the grid is frozen.
Why the role is becoming decisive
For most of chip history, power delivery was a sign-off checkbox and the PDN architect a specialist consulted late. AI silicon changed that. With hundreds of amperes, current ramps of tens to hundreds of amps per nanosecond, sub-volt supplies, and a power network that now spans board to stacked die, voltage droop has become a — arguably the — dominant constraint on what a chip can sustain. The decisions the PDN architect makes at definition and floorplan now set the frequency the chip can hold, the guardband it must carry, and, through silent data corruption, whether a data-center fleet computes correctly.
The PDN architect has quietly moved from a late-stage specialist to one of the people who decides whether a superchip succeeds. Their leverage is in the questions they ask early — and in having an instrument, like PDNLab, capable of answering those questions while the design is still theirs to shape.