Substrate and Interposer

Between the bare silicon die and the printed circuit board sit two layers that rarely get named in a block diagram but determine how a modern chip is powered, connected, and held together: the package substrate and the interposer. This article defines both directly — what each one is, what it is made of, where it sits in the stack, and why high-performance and AI parts increasingly need both.

Where they sit in the stack

A package is everything between the silicon die and the board. Its job is to take connections from the die — which leave the chip at a pitch measured in micrometers — and route them out to the board, where pitch is measured in fractions of a millimeter, while also delivering current in and conducting heat out. The substrate and the interposer are the two routing layers that bridge that enormous change in scale. The substrate is the larger, coarser platform the package is built on; the interposer, when present, is a finer intermediate layer that sits between the die and the substrate.

The substrate

The package substrate is the laminated platform the entire package is built on. It is the layer the die — or the interposer carrying the die — is mounted to, and it is what the BGA solder balls attach to underneath. Its purpose is twofold: to fan out the connections, spreading the dense array of die-level contacts to the much coarser pitch the board can accept, and to provide the mechanical rigidity that holds the assembly flat.

A substrate is an organic laminate. At its center is a rigid core, typically BT resin (bismaleimide triazine) reinforced with woven glass fiber. Above and below the core are build-up layers: thin alternating sheets of dielectric film and patterned copper, laminated on in successive passes, that carry the signal and power routing. The dominant dielectric for these layers is ABF (Ajinomoto Build-up Film). The more build-up layers, the more routing the substrate can carry — and high-end substrates have grown both in layer count and in physical area to keep up with large AI packages. Some advanced substrates are now coreless, dropping the rigid core for a thinner profile and finer features, and glass-core substrates are an emerging alternative prized for flatness and large-panel manufacturing.

The interposer

An interposer is a finer routing layer inserted between the die and the substrate. It exists because some connections — particularly the wide, dense links between two dies sitting side by side, such as a processor and its high-bandwidth memory — are far too fine and too numerous for an organic substrate to route directly. The interposer carries those connections on its surface at near-on-chip density, and uses vertical through-silicon vias (TSVs) to pass the remaining signals and power down to the substrate beneath it. A package built this way — multiple dies sharing one interposer — is what the industry calls 2.5D integration.

The classic interposer is a slab of silicon, fabricated with the same lithography tooling as a chip, which is why it can support extremely fine wiring. On its top surface it carries a redistribution layer (RDL) of thin-film copper traces; running through its thickness are the TSVs, copper-filled vertical vias lined with a dielectric and a barrier metal. Because it is just silicon and wiring with no transistors, this kind is called a passive interposer; an active interposer additionally contains logic. Silicon is not the only option — organic and glass interposers trade some wiring density for lower cost and larger area — but silicon remains the standard for the highest-bandwidth parts.

Why both exist: the pitch problem

The clearest way to understand why a package needs these layers is to look at the change in pitch — the spacing between adjacent connections — as you move from the die down to the board. Connections leave a die only a few micrometers apart and must arrive at the board roughly a hundred times coarser. No single layer bridges that gap; each layer steps the pitch outward, and the interposer and substrate are the two largest steps.

This is also why the two layers are made of different materials. The interposer is silicon precisely because only chip-grade lithography can pattern wiring fine enough for the connections nearest the die. The substrate is an organic laminate because at its coarser pitch, an organic board is far cheaper and can be manufactured at much larger area than silicon. Each layer is matched to the scale of the connections it carries.

	Substrate	Interposer
Position	Beneath the die or interposer; on top of the board	Between the die and the substrate
Primary job	Fan out to board pitch; mechanical support	Dense die-to-die routing at near-on-chip pitch
Material	Organic laminate — BT-resin core, ABF build-up layers, copper	Silicon (also organic or glass); RDL wiring + TSVs
Pitch handled	C4 bumps (~100 µm) out to BGA (~0.4–1 mm)	Microbumps / hybrid bonds (~1–50 µm)
Always present?	Yes, in flip-chip packages	Only in 2.5D / multi-die packages

How power reaches the die: from BGA ball to C4 bump

It is worth tracing the power path through the substrate in detail, because it is not a wire. The substrate collects current from many power BGA balls in parallel, spreads it across internal copper planes, and delivers it to many C4 bumps in parallel. Any single C4 bump is fed by current that entered through dozens of balls and merged inside the planes — the structure is a three-dimensional mesh, not a point-to-point connection.

Vertically, the current climbs through the substrate's layer stackup. A flip-chip substrate is a symmetric laminate — build-up layers, a rigid core, then more build-up layers. From a power ball at the bottom, current rises through laser-drilled, copper-filled microvias in the thin build-up dielectric, then crosses the thick core through mechanically-drilled plated through-holes (PTHs), and climbs more build-up microvias on the die side until it reaches a C4 bump pad on the top layer. The core PTHs are the coarsest, highest-inductance segment of the path, which is one reason coreless substrates — all-microvia stacks, no core — are favored for high-current, low-inductance parts.

The vias are only the risers. The actual distribution happens laterally, in dedicated power and ground planes — low-impedance copper sheets that current spreads across to travel from balls under the package perimeter to bumps under the die center. These planes are also where the substrate performs fan-out for power, reconciling the dense C4 bump pitch (~130–150 µm) with the far coarser BGA pitch (~0.8–1 mm). Where signal vias pierce a plane they leave clearance holes (anti-pads) that locally raise its impedance, so power and signal breakout compete for the same copper.

Most importantly, power delivery is a loop: current flows up the VDD path and returns down the VSS path. The voltage the die receives is degraded by the resistance and, for fast transients, the inductance of that loop — and the loop’s inductance is set by the area enclosed between the outbound and return currents. Designers minimize it two ways: stacking a VDD plane directly over a VSS plane so the outbound and return currents nearly overlap (which also forms a built-in plane capacitor), and interleaving VDD and VSS balls and vias rather than clustering them, so every outbound path has a return path beside it. Power and ground balls are also concentrated in the die shadow, the shortest and lowest-inductance route straight up to the bumps.

Why this matters for power integrity

The substrate and interposer are not only signal-routing layers; they are also part of the power delivery network. Current bound for the die travels up through the BGA balls, across the substrate, through the C4 bumps, up the interposer's TSVs, and finally through the microbumps into the chip. Every one of those segments adds resistance and, more importantly, inductance to the path — and inductance is what converts the fast current changes of a switching AI workload into transient voltage droop. The geometry of these layers, the number and placement of their bumps and vias, and where decoupling capacitance sits within them all shape the impedance the die actually sees. Modeling that path faithfully, from the board through the package to the on-die grid, is exactly the full-stack problem PDNLab is built to solve.