In April 2008, with the industry fixated on the Power Wall — the heat and current limits of scaling — Anasim co-founder Raj Nair argued in EE Times that a quieter, second barrier was already forming behind it: a Power Integrity Wall. His claim was specific and quantitative: inductive L·di/dt noise would roughly double every process generation, the dominant analysis tools would miss it entirely, and scaling would eventually become economically infeasible unless the industry adopted true-electromagnetic power-integrity analysis. Nearly two decades later, AI silicon has walked straight into it. This is a recap of that argument — and why it held.
The wall behind the wall
A decade before the article, leading microprocessor groups were consumed by the Power Wall: supply currents heading past thousands of amperes and power densities compared, only half-jokingly, to rocket nozzles and the surfaces of stars. By 2008 power consumption was the dominant design constraint. But Nair’s point was that something less noticed and less respected sat right behind it — power integrity, the question of how steady the supply voltage stays as the chip switches.
His analogy was domestic: dim your living-room lights too far and a bright scene on the television makes the picture flicker painfully — your attempt to save energy is limited directly by the “light noise” you can tolerate. Integrated circuits are no different. The most fundamental way to save energy is to lower the supply voltage, and how far you can lower it depends directly on the noise on the power grid. Keep transient droops and overshoots within a small fraction — say 5% — of nominal, or performance becomes unpredictable. Power integrity, in other words, is the thing that gates the very energy savings scaling is supposed to deliver.
Two noise terms — and the one the tools ignored
The supply differential in a power grid is degraded by two dominant terms: the static I·R drop through the resistance of the metal, and the dynamic L·di/dt across its inductance (with reflected, propagated, and resonant noise on top). The entire EDA industry, then as largely now, analyzed power grids with variants of the IR-drop methodology. Nair’s warning was that the balance between these terms was shifting fast: because chips compute by switching currents in synchrony with a clock, and clock and switching speeds rise relentlessly with scaling, on-chip di/dt was climbing — making it “imperative that we inspect total power integrity, including L·di/dt and other electromagnetic effects, rather than just I·R drop or its derivatives.”
Roots-of-Two scaling: the derivation
The heart of the article is a deliberately simple scaling exercise. Nair adopted four assumptions reflecting industry trends, calling them “Roots of Two” scaling (0.7 ≈ 1/√2 is the usual per-generation linear shrink):
| Quantity | Scales by | Effect per generation |
|---|---|---|
| Capacitance per area, Ca | √2 | more capacitance per unit area |
| Operating voltage, V | 1/√√2 | down only ~16% |
| Frequency, f | √2 | +40% performance |
| Chip area | 1/√2 | down only ~30% — the rest spent on more circuits |
Under these assumptions, active power stays constant generation to generation — the economic bargain of Moore’s Law:
From there the inductive-noise term follows in four steps:
- Power is constant and V drops by 1/√√2, so the average current scales by 21/4.
- Frequency rises by √2, so di/dt scales by 21/4·√2.
- Each side of the (square) die shrinks by 1/21/4; with the same metal fraction, the number of parallel power buses per side falls by 1/21/4, so the effective inductance rises by 21/4.
- Multiply inductance by di/dt:
Inductive noise doubles every scaled generation — even though total power is flat. Nair was candid that the exact factors were “highly simplified and by no means accurate, but the trend surely is.” To make it concrete: take L·di/dt noise at ~9 mV in the 180 nm generation; following the trend, the 45 nm node sees about 16× that — roughly 144 mV, around 15% of the supply differential, or about 3× the entire allowed noise budget. IR-drop tools, by construction, see none of it. Independent academic PEEC studies of power grids had already shown the same quadratic rise of inductive noise with faster rise times.
The crux. Constant-power scaling does not mean constant power-integrity. Faster edges move charge through less metal and from less nearby capacitance, so the dynamic droop climbs exponentially while the voltage budget it must fit inside shrinks.
Why the usual fixes don’t work
Nair then anticipated the two reflexive responses a block designer would reach for — and showed both fail:
- “Copy exactly.” Allocate the same fraction of metal to the power grid as last generation (“it worked before”). The derivation says this yields twice the inductive noise — a torpedo that surfaces only after fabrication.
- Widen the wires. Best-practice IR-drop reasoning says higher average current needs more grid metal; constrained by routing, designers often widen the straps rather than tighten the pitch, and IR-drop tools duly show improvement. But widening metal does little — sometimes even slightly negative — for L·di/dt, and high-frequency current crowds into the low-inductance parts of the bus anyway.
Both lean on prior experience instead of verification — and, as in finance, past performance is no guarantee of future results. The root cause Nair identified was a tooling gap: the absence of efficient, accurate ways to run rapid, comprehensive, true-electromagnetic simulations of IP blocks, multi-core chips, and whole delivery systems. Notably, he cited published work showing that including on-chip inductance actually optimizes power-metal area — about 30% less metal at 90 nm and up to 60% at 45 nm — so the EM-aware approach is not just safer, it is more efficient.
The Power Integrity Wall
Put together — exponentially rising L·di/dt, no tools to simulate it, ever-lower operating voltages, device variation at nanoscale nodes, and low-power techniques like power gating that worsen transient noise in non-obvious ways — Nair argued these compound into yield spread and, ultimately, the economic infeasibility of further scaling. A barrier “as severe, if not more severe, than the Power Wall.” His sharpest line: low-energy design does not mean fewer power-integrity problems; it is often the opposite. Sub-volt chips with real integration and performance are only feasible if the very narrow allowable noise band on their supplies is thoroughly understood and verified — the alternative being to abandon efficient digital logic for noise-tolerant current-mode circuits.
The solution path he laid out
The article closed with a concrete, non-disruptive flow — essentially a shift-left, EM-aware power-integrity methodology, built around Anasim’s pi-fp:
- Begin floorplanning for power integrity at the architectural stage.
- Synthesize low-inductance, symmetric IP-core and global power networks.
- Optimize grid dimensions with true-electromagnetic simulation and set an initial on-chip decoupling-capacitance strategy.
- Optimize floorplan placement to minimize total-noise band, lowering operating voltage while still meeting timing.
- Run static IR-drop to catch hotspots and electromigration stress.
- Add system components (package capacitors, supply connectivity) and re-run dynamic, true-EM noise analysis with improved block current profiles; tune interconnect and decap accordingly.
Arriving on schedule
Eighteen years on, the prediction reads less like a warning and more like a description. AI accelerators draw hundreds of amperes at 700 W and beyond, with die-level current ramps of 10–100 A/ns; supplies sit near and below a volt; and hyperscalers now treat silent data corruption — the fleet-level signature of droop crossing Vmin — as a first-order operational risk. The exact constants in the Roots-of-Two derivation were never the point; the trend was, and the trend held. L·di/dt, not I·R drop, is now the term that decides whether advanced silicon computes correctly.
What was missing in 2008 was the tooling to act on the diagnosis. That is what pi-fp began and what PDNLab is the commercial evolution of — a true-electromagnetic, continuum power-integrity environment that lets designers run exactly the six-step flow above, at the planning stage, before the grid is frozen in metal. The Power Integrity Wall arrived on schedule. The difference now is that you can see it coming.
Adapted and recapped from Raj Nair, “A Power Integrity Wall follows the Power Wall,” EE Times, April 8, 2008. Original references include R. Nair & D. Bennett, “Power Integrity and Energy-Aware Floorplanning” (SoCCentral, 2008); R. Nair, “Emerging Directions for Packaging Technologies,” Intel Technology Journal 6(2), 2002; and academic studies of on-chip inductance in power distribution (Muramatsu et al., ISPD 2005; Srivastava et al., ISQED 2005).