A modern accelerator’s power delivery network has to hold a supply rail near 0.75 V while the die beneath it draws close to a thousand amperes — and while that draw rises and falls by a large fraction of its value in well under a nanosecond. No single wire and no single metal layer can meet all of those demands at once, because the requirements pull in opposite directions: carrying hundreds of amps across millimeters wants thick, wide, sparse metal, while reaching every one of a hundred billion transistors wants fine, dense metal. What actually delivers the power is therefore a graded network — resistive where it must be fine-pitched, low-inductance where it must respond quickly — and its design is a negotiation among resistance, inductance, capacitance, current density, and the routing tracks left over for signals. Anasim’s Π-FP represents that whole network with a comparatively compact model: a hierarchy of two-layer symmetric transmission-line grids. This article walks the full path — the physical network, the flow that builds it, and the model that abstracts it — and shows why “two layers” is a statement about which physics governs dynamic failure, not a discarding of the other sixteen.
Three descriptions of one object. The same PDN can be described physically (a graded metal fabric), by implementation (rings, stripes, rails and vias authored in a tool like Innovus), and behaviorally (a network of R, L and C solved as transmission lines in Π-FP). These are not three different networks; they are one network seen at three resolutions, and each description keeps precisely the quantities its question needs. Holding those three views together is what makes the abstraction legible.
Part A — The physical network and what it must achieve
The quantity under control is impedance, not voltage
It is tempting to state the PDN’s job as “keep the voltage steady,” but that framing hides the hard part. The supply is loaded by switching logic that draws current in bursts spanning an enormous range of frequencies — from the slow envelope of a workload ramping up over microseconds, down to the individual clock edges that switch charge in tens of picoseconds. Every one of those current components develops a voltage across whatever impedance the network presents at that frequency. So the real specification is a statement about impedance: the PDN must present an impedance low enough, at every frequency the load excites, that the resulting voltage deviation stays inside the rail’s tolerance band.
This is captured by the target-impedance methodology that PI engineers use as a first cut. If the rail tolerance is ΔV and the worst-case transient current step is ΔI, the network must satisfy Z(f) ≤ ΔV / ΔI across the band of interest. Put numbers to it: a 0.75 V rail with a 5% budget allows about 37 mV of droop; a transient step of a couple hundred amps then demands a target impedance on the order of a few tenths of a milliohm. What makes this genuinely difficult is that the bound is not a DC number — it must hold roughly flat from DC out to the hundreds of megahertz where fast workload transients still have spectral energy. At DC the impedance is pure resistance, and the problem is one of metal cross-section. As frequency climbs, inductance and capacitance take over, and the impedance profile develops resonant peaks that a purely resistive analysis cannot even see. Shaping that impedance-versus-frequency curve to stay under the target, everywhere, is what power delivery design actually is.
Why the network is graded across many layers
The reason a PDN spans a dozen or more metal layers is not redundancy; it is that resistance and reach cannot be satisfied by the same geometry. Sheet resistance is fixed per layer by the metal’s thickness and resistivity, and it varies by more than an order of magnitude across the stack: the ultra-thick top metals sit in the low tens of milliohms per square, while the thin local layers near the transistors are in the range of hundreds of milliohms per square. Current entering at the package must travel millimeters laterally to reach the far side of the die, and doing that on thin metal would burn an unacceptable fraction of the supply in IR drop before the current ever reached a cell. So the long-haul lateral transport is assigned to the thick top layers, where sheet resistance is lowest. But those same thick layers are coarse — wide wires on a large pitch — and cannot reach into the dense interior of a standard-cell row. The network therefore steps down in granularity: current is handed from the thick global layers, through arrays of vias, to progressively finer intermediate and local grids, and finally to the thin M1 rails that run directly along each row of cells. Each step trades resistance for reach, and the via arrays between steps must themselves be wide enough to carry the current without becoming the bottleneck.
A structural fact follows that is easy to miss and important to state plainly: only a subset of the metal layers carry power and ground at all. The remaining layers are given over to signal routing. Power is picked up and re-meshed at a few discrete “stations” in the stack — a global grid high up, one or more local grids lower down — and at each station the structure is, locally, just two orthogonal layers of stripes forming a mesh. The full fabric is a hierarchy of such meshes, connected vertically.
This is the point worth dwelling on, because it is exactly where the “two layers” objection usually goes wrong. Π-FP does not average a dozen layers into two. It represents the design as a hierarchy of two-layer grids — a global grid on, say, M13/M14, tapped by several local grids on M7/M8, each defined with its own widths, pitch, and material parameters, and all of them connected through the via interfaces. The two-layer mesh is the modeling unit, and you compose as many of them as the physical design has distinct grid stations. A design with a global distribution grid feeding four block-level local grids is four local two-layer grids plus one global two-layer grid, wired together — not a single flattened pair.
Static drop, dynamic droop, and electromigration
The impedance profile fails in three physically distinct ways, and separating them is the key to understanding why more than one analysis tool exists. The first is static IR drop: the average current drawn by a region, multiplied by the resistance of the path back to the supply, produces a steady voltage loss. It is governed entirely by resistance and metal cross-section, its budget is typically one to a few percent of the rail, and it is fixed by widening wires, adding via arrays, and densifying the mesh. It is a DC problem, and a resistive solver captures it completely.
The second failure is dynamic droop, and it is the one static analysis cannot see. When a large block of logic switches, it demands a current step that the network cannot supply instantaneously. For the first fraction of a nanosecond the charge comes from on-die decoupling capacitance sitting right next to the load. As that reservoir depletes, current has to be pulled from farther away — across the on-die grid, up through the package — and the inductance of that path limits how quickly it can ramp. The interaction of the package’s series inductance with the die’s decoupling capacitance forms a resonant tank, the chip-package resonance, which typically sits in the range of tens to low hundreds of megahertz. A current transient with energy near that resonance drives the supply into a damped oscillation — the rail overshoots and rings, not merely sags. Because the governing term is L·di/dt, the magnitude of the droop depends on how fast the current changes, not only on how large it is. This is the regime the transmission-line treatment in Π-FP is built to resolve, and it is inherently spatial as well as temporal: the disturbance propagates across the grid, so different locations on the die see different droop at different instants.
The third failure, electromigration, is a reliability limit rather than a functional one. Sustained high current density gradually displaces metal atoms along a wire, eventually thinning it to an open or bridging it to a neighbor; the mean time to failure falls steeply with current density (Black’s law, roughly MTTF ∝ J−n·exp(Ea/kT)). It is addressed by capping the current per unit width — again through wider wires and larger via arrays — and it is checked over the chip’s operating lifetime rather than over a clock cycle.
The division of labor follows directly. Resistive signoff tools such as Cadence Voltus and Ansys RedHawk own the first and third: they carry the full extracted geometry and answer “is any node too low on average, and is any wire carrying too much current density.” The middle failure — the inductive, resonant, propagating transient — is a different question, answered by a different reduction of the same network. That reduction is Π-FP.
The interleaved mesh, and why symmetry lowers inductance
On any power-bearing layer the stripes alternate supply and return at a fixed pitch — VDD, VSS, VDD, VSS — running in one direction, with the layer below running the orthogonal direction and vias placed at every crossing of like nets. Understanding why that alternation is universal requires thinking about inductance correctly. Inductance is not a property of a wire in isolation; it is a property of a current loop, and it scales with the area that loop encloses. The relevant loop for a supply current is the path out along a VDD conductor and back along the nearest VSS conductor. Placing a VSS stripe immediately beside every VDD stripe makes that loop as thin as the geometry allows, which minimizes its enclosed area and therefore its inductance. This is reinforced by the physics of high-frequency return current: at the frequencies that dominate droop, return current does not spread diffusely through the ground network but crowds onto the conductor closest to the outgoing current (the proximity effect), so the effective return for each VDD stripe genuinely is its adjacent VSS neighbor. Tight interleaving is not a layout convenience; it is the direct consequence of minimizing loop inductance and controlling the return path.
That physical picture is what licenses the pairing abstraction, and it dissolves a common objection.
The objection
“Real grids are interleaved — a single VSS stripe returns the current of the VDD stripes on both sides of it. Π-FP models the grid as isolated VDD/VSS pairs. So the pairing model doesn’t reflect how modern grids are laid out.”
Why the two descriptions agree
A uniform interleaved array is a tiling of adjacent pairs. Under the symmetric, equal-and-opposite excitation the grid actually sees, the midplane of each shared VSS stripe is a plane of symmetry — a virtual boundary — so the array decomposes into independent VDD/VSS pairs by superposition. The interleave is what makes the shared return exact, which is precisely what the pairing model assumes. The two descriptions are the same electromagnetic unit cell drawn at different scales.
The manual’s figures draw a single pair; the physical grid tiles that pair across the die. “Isolated pair with a gap” and “dense uniform interleave” are not competing structures — they are the same repeating cell, and the model is built on the cell.
Part B — How the grid is built in Innovus
Power planning is one of the first operations in the place-and-route flow, done at floorplan stage before standard cells are placed, because the grid is metal that everything downstream must route around. Engineers do not draw individual power wires; they author a compact recipe — nets, layers, widths, pitches, and via rules — and the tool’s power-ground engine synthesizes the geometry. Tuning that recipe is, in effect, shaping the impedance profile discussed in Part A: a wider strap or a tighter pitch lowers both resistance and inductance at the cost of routing tracks, and every choice trades one budget against another. Before the flow, the vocabulary, since the rest of the discussion depends on it:
| Term | What it is, and what it controls |
|---|---|
| Pad / bump (C4) | The package-to-die power contact. Flip-chip C4 bumps form a two-dimensional array across the die; they are the discrete points where current enters, which is why lateral spreading on the top metal matters so much. |
| Ring | A wide closed loop of VDD and VSS metal around the core or a block, fed directly from the bumps — the local low-impedance reservoir that the stripes tap into. |
| Stripe / strap | A straight power or ground line crossing the core at a chosen width and pitch. Two orthogonal sets of stripes form the mesh; their width sets resistance and EM headroom, their pitch sets both granularity and, as Part C shows, the grid’s wave behavior. |
| Rail / followpin | The thin M1 line that follows a standard-cell row directly into the cells, with VDD at the top of the row and VSS at the bottom. The last, most resistive hop. |
| Via array / pillar | Clusters or vertical stacks of vias at same-net crossings. Pillars carry current between grid stations at low resistance and spread it over enough vias to satisfy electromigration. |
| Pitch / width / spacing / offset | Center-to-center period of the stripes / the strap thickness / the edge-to-edge gap between adjacent nets / the lateral shift of one layer’s stripes relative to another, used to manage inter-layer coupling. |
| PG blockage | A keep-out region that prevents the tool from placing power-ground metal where signal routing is too congested to give it up. |
| Power domain (UPF/CPF) | A region operating at a given supply, possibly gated or switchable. The number of independent domains sets how many separate grids the plan must build. |
With the terms in place, the build is a fixed sequence. Shown in Cadence Innovus, with the Synopsys ICC2 equivalents noted; exact syntax varies by tool version, but the structure is universal:
Two consequences of this flow matter for what follows. First, stripes deliberately do not pave the layer. A 0.6 µm strap on a 9 µm pitch occupies only a small fraction of the available tracks; the intervening space is left open for the router to place signals, and on the intermediate layers a power grid typically consumes only ten to twenty-five percent of the metal. The pitch and width are chosen to balance the impedance target against that routing budget, and if the design fails to route, the grid is thinned or its pitch relaxed. Second, and central to this article: the width, pitch, spacing, and layer assignment an engineer types into add_stripes are the very quantities Π-FP consumes. The abstraction is not fed an approximation of the layout — it is fed the layout’s defining parameters directly.
When power planning completes, the tool emits the physical description the rest of the flow reads: DEF for the exact coordinates of every stripe, rail, and via; GDSII for the mask polygons; SPEF for the extracted resistance and capacitance; the technology LEF for layer thickness, sheet resistance, and via rules; and UPF/CPF for the power domains and their voltages. Π-FP takes this physical description and returns the R, L, and C behavior the geometry implies — the dynamic response that the geometry alone does not make visible.
Part C — The Π-FP abstraction, derived from the manual
Π-FP is a true-physical, SPICE-like solver: it retains resistance, inductance, and capacitance and integrates the actual transmission-line equations across the grid. What makes it tractable at full-chip — indeed multi-chip, package, and board — scope is that it represents the grid as symmetric transmission-line pairs, which collapses the problem to a size a solver can handle in minutes. The reduction rests on three ideas from the manual, taken in turn.
1 · Symmetry, and solving a single rail
When a VDD/VSS pair is driven symmetrically, the supply and return carry currents that are equal in magnitude and opposite in sign, and the voltage disturbances on the two rails become mirror images. The manual’s Figure 1.2 makes this concrete by contrasting where the current source attaches: connect it at the symmetric point A and the waves on the two rails are exact opposites; connect it at the asymmetric point B and that relationship breaks. Two things follow from the symmetric case. First, the equal-and-opposite currents in the tightly spaced pair produce magnetic fields that largely cancel in the far field, so the pair barely couples to neighboring nets — the same physical benefit that tight interleaving buys in the real grid. Second, and computationally decisive, because the return rail is the mirror of the supply rail, there is no need to solve both: Π-FP solves a single, uncoupled partial differential equation for one rail and infers the other. The uniform interleave established in Part A is exactly the condition that makes this mirror relationship hold rather than merely approximate.
This is also why the manual forbids singly-routed power or ground wires. A lone conductor with no adjacent return has no mirror; its return current wanders through distant metal, its loop area and inductance are large and ill-defined, and it couples strongly to whatever it runs beside. The symmetric-pair method has nothing to reduce in that case. Robust physical grids avoid singly-routed supply metal for the same electrical reasons, so the modeling requirement and good design practice coincide.
2 · The distributed element and the telegrapher’s equations
To turn the grid into equations, the manual treats each pair as a distributed line and examines a short section of length dx (Figure 1.3). Current I enters the section and I + dI leaves it; the difference is drawn off by a shunt branch containing two things distributed uniformly over the block’s area — the load current the block sinks, written as a per-unit-length source I0, and the decoupling capacitance C that sits between the rails. Applying Kirchhoff’s laws to that section yields the two coupled relations that govern everything downstream:
Two modeling choices in these equations deserve comment. The load is a distributed current source: rather than modeling each gate, the user supplies one current profile per block — obtained from a gate- or transistor-level simulation — and spreads it uniformly over the block’s footprint. This is legitimate precisely when the block is well connected to the grid, with many tap points spread symmetrically across its area, so that no single point dominates the injection. The decoupling capacitance is treated the same way, distributed uniformly. Worst-case noise, the manual notes, is produced when many closely spaced blocks switch simultaneously — the coherent case the pair model is designed to resolve.
Equations (1.1) and (1.2) are the standard telegrapher’s equations, and reading them together shows the pair behaving as a transmission line with a characteristic impedance set by the ratio of its inductance to its capacitance. The resistive term dictates how the line loses energy; the L and C terms dictate how disturbances propagate along it.
3 · From RLC to a propagating wave
The conceptual payoff comes when the resistive term is small compared with the inductive one — the low-resistance condition that the wide, thick global grid satisfies. In that limit the pair becomes a nearly lossless line, and combining (1.1) and (1.2) gives a wave equation for the supply. This is the crucial reframing: on a low-resistance grid the disturbance does not simply sag and settle, it travels.
The choice of when this regime applies is not incidental; it is why the transmission-line treatment is directed at the global grid rather than the local rails. A conductor behaves resistively (diffusively) when its series resistance dominates and inductively (as a wave) when ωL exceeds R over the length in question. The thin, high-resistance M1 rails stay in the RC regime; the wide, thick, low-resistance global straps cross into the LC regime at exactly the fast transient frequencies that cause dynamic droop — which is where the manual’s Equation 2.1 explicitly begins, “the wave velocity across a low resistance grid.” Solving the wave, and relating its velocity to the geometry, gives:
That last relationship has a practical reading. The resonant wavelength of the noise, compared against the die dimension, determines whether droop is roughly uniform across a block or varies strongly from edge to edge. Two grids with identical DC resistance but different pitch can therefore have quite different dynamic signatures — a distinction invisible to static analysis but captured directly here through s.
add_stripes.4 · The netlist: the global-grid G element
Everything above collapses into a single line of input. One G statement declares a two-layer grid, and every field in it is a physical power-planning quantity rather than an abstract fitting parameter:
| Parameter | Meaning (manual) | Units | Where it comes from |
|---|---|---|---|
| chip_width / height | die extent | cm | the floorplan die area |
| tline_wire_width (w) | width of the supply/return straps in the two-layer grid | cm | add_stripes -width |
| tline_periodic_space (s) | center-to-center distance of a supply/return pair | cm | add_stripes pitch |
| sheet_resistance (Rs) | sheet resistance of the grid metal | Ω/□ | the technology LEF for that layer |
| inductance (L) | loop inductance per unit length of the pair | H/cm | geometry / a field solve — the term IR tools discard |
| default_cap (CA) | area capacitance where no block is defined | F/cm² | the dielectric stack / extraction |
Reading the manual’s example clarifies the scale involved: a 3.5 mm × 3.8 mm die, straps 20 µm wide on a 90 µm pair pitch, a sheet resistance of 0.025 Ω per square, a loop inductance of 8 nH/cm, and an area capacitance of 12.5 nF/cm². Every one of those figures is a decision or an extracted property from physical design; none is invented for the model. The width and pitch come straight from add_stripes; the sheet resistance comes from the technology file; the inductance and area capacitance come from the geometry, obtained analytically or from a field solver. The abstraction’s inputs are the layout’s own parameters, which is what makes the mapping between the physical grid and the model exact rather than heuristic.
5 · Composing the hierarchy
Because Π-FP is a multi-grid tool — the manual states it can simulate any number of connected transmission lines and floor-plan grids — the real stack is represented not by one G element but by several, wired together. A global grid, defined by its own width, pitch, and material parameters, feeds a set of local grids each defined by theirs, and the connections between them model the via-pillar taps. This is the direct answer to “you are only modeling two of eighteen layers”: the design is modeled with as many two-layer grids as it has distinct grid stations, each carrying its own distributed load blocks and decoupling capacitance, and the hierarchy is reconstructed by connecting them. The two-layer pair is the atom of the model; the molecule is the composed hierarchy.
Part D — What the model keeps, and what it sets aside
A model earns trust by being explicit about its reductions. Π-FP retains, at each level of the hierarchy, the lateral redistribution mesh that carries the dominant share of the on-chip voltage variation; it retains the loop inductance of the adjacent VDD/VSS cell, which is the term resistive signoff cannot see and the driver of dynamic droop; and it retains the wave behavior that makes droop a propagating, spatiotemporal phenomenon rather than a single worst node. Its use of two orthogonal layers is faithful rather than reductive, because a mesh genuinely is two orthogonal sets of stripes — the two-layer count describes the unit cell, not a lossy compression of the stack.
What it sets aside is equally deliberate. Vertical via-stack resistance is treated as near-ideal within a grid, and the manual justifies neglecting the horizontal drops on other layers relative to the dominant global mesh — a defensible approximation for global dynamic behavior, though not the right tool for cell-level static IR sign-off, where every via matters. Signal metal is treated as dielectric and not modeled. The exact polygons, via counts, and design-rule detail are replaced by effective per-length R and L and per-area C. Electromigration is out of scope by construction, because it is a current-density reliability question rather than a dynamic-voltage one. None of these omissions is accidental; each removes a quantity that governs static or local precision while preserving the quantities that govern the transient.
| Aspect | Treatment in Π-FP |
|---|---|
| Lateral mesh(es) | Kept faithfully at each level of the hierarchy — the dominant redistribution path. |
| Loop inductance L | Kept — the term resistive signoff cannot see; the driver of dynamic droop. |
| Wave propagation | Kept — spatiotemporal droop and resonance across the die. |
| Two orthogonal layers | Faithful — a mesh is two orthogonal stripe sets; the count is a unit cell, not a squash. |
| Via-stack resistance | Abstracted — near-ideal within a grid; adequate globally, not for cell-level signoff IR. |
| Signal metal | Dropped — treated as dielectric. |
| Polygons / via counts / DRC | Dropped — replaced by effective per-length R, L and per-area C. |
| Electromigration | Out of scope — a current-density reliability check, handled by resistive tools. |
The reduction is best understood as a complement to resistive signoff rather than a competitor to it. Voltus and RedHawk keep the full geometry to answer the static and reliability questions with local precision; Π-FP keeps the R, L, C and wave physics to answer the dynamic question at full-chip scale and early enough to change the floorplan. The two tools keep the mirror-image halves of the same network because they are asked mirror-image questions.
The direction of travel makes the dynamic question more pressing, not less. As switching currents grow steeper, the inductive term in Equation 1.1 becomes the binding constraint on the supply. Backside power delivery, now entering advanced nodes, shortens the vertical path and lowers static IR drop — but in doing so it removes resistive damping from the network, which raises the effective quality factor of the package-die resonance and makes the rail ring harder for a given transient. That pushes leading-edge designs further into the low-resistance, wave-dominated regime that Equations 2.1 through 2.5 describe, and that resistive analysis was never built to resolve. The abstraction that looks aggressive today is aligned with where the physics is heading.
Related reading
- Defining the Power Grid: From Synthesis to the First Stripe — the power-planning stage in the place-and-route flow.
- Reverse-Engineering the Power Grid — extracting a real fabricated PDN from GDSII and testing the two-layer-pair abstraction against it.
- Inside HBM: The L·di/dt Droop It Hides — the same inductive, resonant physics off-die.
- Anasim Corp., “Π-FP User Manual,” 2015. pi-fp-man-2015.pdf — Figures 1.2, 1.3, 2.3 and the global-grid netlist referenced throughout.