The Streaming Multiprocessor, or SM, is the fundamental unit compute block of modern AI. 144 of these SM tiles are packaged into a single die that we call the NVIDIA® H100 GPU. As AI becomes the backbone of the economy and a primary driver of modern technology innovation, power-delivery modeling and visualization at the level of a single SM becomes crucial: each core operates at a ~0.6 V supply, where even a hundred millivolts of local droop is the difference between a clean compute cycle and a timing failure.

Anasim's PDNLab is a power-integrity simulator: it represents an on-chip power-delivery network as a distributed RLC grid driven by current sources at each switching block, and solves for the voltage waves that propagate across that grid as the sources turn on and off. The output is a time-resolved map of local supply voltage — where the grid droops, by how much, and how quickly it recovers.

In this article, we model a single H100 SM core in PDNLab and evaluate the on-chip local power grid under two AI workload activation patterns. The model itself — floorplan, current-source partitioning, and power grid — is built from publicly available information (the H100 whitepaper, microarchitecture publications, and engineering-grade area estimates) and is identical for both scenarios. What changes between scenarios is the temporal firing pattern of the four sub-cores:

• Scenario 1 — Lockstep firing. All four sub-cores fire their WGMMA bursts at the same instant. Worst-case di/dt, used historically for sign-off margining.
• Scenario 2 — Column-wise temporal excitation (experimental probe). The two edge sub-cores (SC0, SC3) fire their tensor burst first; the two center sub-cores (SC1, SC2) fire next. Total charge and SM-level peak current are held constant — only where on the die the current lands, and when, is changed.

The result is a side-by-side view of how much of the SM’s observed droop is a property of the grid and decap versus a property of the scheduling pattern imposed on it. The rest of this note walks through the model construction, defines both scenarios with the same per-source amplitudes and pulse shapes, and compares their droop signatures on the same CORE grid.

Semi-global grid (M7/M8) — the surface the four Tensor Cores see directly. Peak droop ~100 mV during lockstep burst.

Die-wide global grid (M14/M15) — how the same transient propagates up through the 36 stitching vias and out into the package-facing rail.

Before any power-grid simulation is possible, the SM has to be defined as a physical, electrically meaningful object: how much die area it occupies, how much current it draws on average, what blocks live inside it, and where those blocks sit relative to each other. This section walks through that definition in four steps — SM Core Size sets the spatial budget, SM Core: Power and Current sets the electrical budget, SM Subblocks enumerates the architectural inventory inside that budget, and SM Floorplan Model arranges those subblocks into the floorplan PDNLab will simulate.

SM Core Size

NVIDIA® does not publish a per-SM area number directly, so we estimate it. The GH100 die is roughly 814 mm². After deducting the L2 cache, HBM PHY, NVLink, and other non-SM area, roughly 60% of the die is occupied by the 144 physical SMs:

A_SM ≈ 814 mm² × 0.60 ÷ 144 ≈ 3.39 mm²

Approximating the SM as a square gives a side length of 1.84 mm, so the working canvas is 1.84 mm × 1.84 mm. Every block dimension below is sized against this budget.

SM Core: Power and Current

NVIDIA® publishes the SXM5 board TDP (700 W) and a base clock of 690 MHz, but no per-SM power number. The 700 W is the peak-load figure; at the base-clock operating point with a ~0.6 V core supply, board power is on the order of ~350 W. Roughly 60% of that is consumed by the SMs, with the remainder going to HBM3, NVLink and PCIe interfaces, the L2 cache, control logic, voltage-regulation losses, and leakage. Spread across the 144 physical SMs, the per-SM average is:

P_SM ≈ (0.60 × 350 W) ÷ 144 ≈ 1.458 W

At a 0.6 V core supply, the average per-SM current follows:

I_avg ≈ 1.458 W ÷ 0.6 V ≈ 2.43 A

The 690 MHz base clock corresponds to a 1.45 ns clock period, so the charge drawn from the local PDN by one SM in one clock cycle is:

Q_cycle ≈ 2.43 A × 1.45 ns ≈ 3.52 nC

That 2.43 A is the average. The instantaneous current swings between near-idle leakage and full tensor-pipeline activity within a single clock cycle, and the local on-die power grid has to absorb that swing without the supply drooping out of spec. At a 0.6 V rail, even a 100 mV droop is a 17% supply collapse — and gate delay degrades faster than linearly near threshold, so the timing margin shrinks faster than the supply does. That is why the low-DVFS operating point is the interesting one to study, not the peak-power one.

SM Subblocks

An SM is divided into four sub-cores (NVIDIA® calls them "processing blocks"). This is documented in the H100 whitepaper, in Choquette's IEEE Micro paper on Volta [2], and in Barnes et al.'s HPCA 2023 paper on Hopper [4]. Each sub-core contains its own warp scheduler, dispatch unit, register file, and execution units. The L1 instruction cache, the unified L1D / shared memory, the texture units, and the Tensor Memory Accelerator are SM-shared.

Per sub-core, the compute inventory is: 32 FP32 cores, 16 INT32 cores, 16 FP64 cores, 1 fourth-generation Tensor Core, 8 LD/ST units, and 4 SFUs. (NVIDIA® refers to these execution units as “cores” in the whitepaper — e.g. “CUDA cores” for the FP32 / INT32 / FP64 units.) The register file is 64 KB per sub-core (256 KB per SM total), and microbenchmarking work by Jia et al. [3] showed that this 64 KB is physically split into two banks per sub-core, for eight banks per SM. Barnes et al. confirmed the same banking holds through Hopper.

Putting that together, one SM contains:

SM Floorplan Model

The diagrams NVIDIA® publishes are block diagrams, not floorplans. There is no public die-shot of the GH100 with labeled SM internals, so the spatial arrangement we use is engineered, not measured. What we can do is fix the topology from the published sources, fix per-block area from engineering estimates, and arrange the blocks consistent with the routing physics that motivates NVIDIA®'s partitioning in the first place.

The published block diagrams are not arbitrary either. Comparing the Volta and Ampere SM block diagrams against the labeled die-shots that did get published for those generations [2, 3], the diagrams turn out to be reasonably faithful to the relative size and ordering of major blocks — the SMEM macro really does sit on one edge, the sub-cores really do appear as a row, the I-cache really does sit opposite the SMEM. They are stylized, but spatially indicative. We therefore treat the H100 block diagram as a usable starting point for relative arrangement, even if exact micron-level coordinates are unknown.

The approximate per-block area percentages we anchor against come from a combination of SRAM density rules and Volta/Ampere die-shot studies:

• Register file: 22–30% of SM area
• Shared memory / L1D: 18–25%
• Tensor Cores (combined): 15–22%
• FP32 + INT32 cores: 8–12%
• FP64 cores: 6–10%
• LD/ST + SFU: 5–8%
• Texture: 3–5%
• L1 instruction cache: 2–4%
• Schedulers + dispatch: 3–5%
• TMA: 1–3%
• Routing and clocking: 10–20%

Current sources

PDNLab models the SM as a netlist of independent current sources — one per modeling primitive, not one per architectural block. Two rules drive how we collapse the inventory above into sources:

• Merge blocks that are always co-active in the same cycle and physically adjacent. Their currents superpose at the same node anyway, so splitting buys no spatial resolution. The warp scheduler and dispatch unit merge into a single sched_dispatch source. The 8 LD/ST units and 4 SFUs merge into a single ldst_sfu source.
• Keep separate blocks that are independently gated by the workload. FP32 and INT32 stay separate because Hopper supports concurrent issue. FP64 stays separate because HPC kernels load it without firing the AI pipes. The Tensor Core stays separate because it dominates peak current. The two register-file banks stay separate so their current can cluster spatially next to the lanes each bank feeds.

That gives 8 current sources per sub-core (sched_dispatch, rf_bank0, rf_bank1, fp32, int32, fp64, tensor, ldst_sfu) plus 4 SM-shared sources (l1_icache, smem_l1d, tex, tma), for 36 current sources per SM.

Within-tile placement

With the caveat that we do not have a labeled die-shot to validate against, we arrange the sources inside each sub-core column tile in a vertical stack from top (facing the I-cache stripe) to bottom (facing the SMEM/L1D stripe):

1. sched + dispatch — top of the tile, directly under the I-cache stripe so its instruction-fetch path is short.
2. RF bank 0, then FP32 and INT32 — bank 0 sits adjacent to the cores it feeds. NVIDIA® partitioned the SM into sub-cores “to reduce area and energy-consumption” [4], and the energy savings come from short operand wires; this stack reflects that.
3. RF bank 1, then FP64 and the Tensor Core — bank 1 feeds the AI/HPC pipes. The Tensor Core occupies the largest single area inside the tile, since at the per-SM level it accounts for roughly 18% of the area.
4. LD/ST + SFU — bottom of the tile, directly above the SMEM/L1D stripe so its operand traffic drops straight down into the shared memory bank below it.

These are physics-of-routing placements, not dataflow placements. Barnes et al. note that NVIDIA® partitioned the SM into sub-cores "to reduce area and energy-consumption" — the energy savings come from short operand wires. So RF banks sit next to the units they drive, the schedulers sit next to their instruction source, and the LD/ST units sit next to their memory destination.

SM-level placement

At the SM level we arrange the four sub-core tiles as four columns side-by-side (a 1×4 grid), spanning the full SM width between the I-cache stripe at the top and the SMEM/L1D stripe at the bottom. We chose 1×4 over 2×2 for two reasons. First, it matches the literal reading of the H100 whitepaper block diagram, which draws the four processing blocks as four columns with the I-cache above them and the SMEM/L1D below. Second, in a 1×4 layout every sub-core sits the same vertical distance from both the I-cache and SMEM stripes — instruction fetch and shared-memory access are equal across all four sub-cores. A 2×2 layout would put the top two sub-cores closer to the I-cache and farther from SMEM (and vice versa for the bottom two), which is harder to justify when the shared SRAM macros are stripes rather than centered spines.

Below the SMEM stripe, a thin perimeter strip carries the texture units (left) and the TMA (right). New in Hopper, the TMA performs asynchronous DMA between global memory and shared memory, so placing it directly below the SMEM macro keeps its dominant data path short.

None of these placements are confirmed by NVIDIA®. They are an engineered arrangement consistent with the published block diagrams and with the routing-physics rationale that motivates NVIDIA®’s sub-core partitioning [4]. A real GH100 floorplan may differ in the details. The topology and per-block area, however, are anchored to public sources and should be representative.

Floorplan diagram

The vertical stack closes exactly to 1.840 mm: 0.060 mm I-cache + 1.300 mm sub-core row + 0.390 mm SMEM/L1D + 0.090 mm TEX/TMA strip. The four sub-core tiles each occupy 0.460 mm × 1.300 mm. Total area sums to 3.386 mm², matching the 1.84² per-SM area we derived from the die budget at the top.

The H100 is fabricated on TSMC’s 4N process — a customized 5 nm-class node with up to 15 metal layers. Power on a die this size is delivered in two tiers: a global grid on the uppermost thick-metal layers (M14–M15) that distributes power across the whole die, and per-block semi-global grids on the middle layers (M7–M8) that fan power down through the via stack to the standard cells. In this study we model both the per-block semi-global grid and the die-wide global grid, including the via stitching that couples them, so we can observe how local transients propagate between tiers.

For clarity, the two modeled grid regions used in the SM simulations are represented with aggregated per-region impedances in PDNLab. These lumped parameters capture the dominant series resistance, inductance and the effective local capacitance that shape transient droop at the SM scale:

These values are aggregated model parameters (not raw per-via numbers) chosen to reproduce the observed transient impedance and charge-storage behavior in the targeted SM footprint; the via stitching that connects the two tiers is modeled explicitly so charge exchange between `sm_core` and `sm_global` appears in the time-domain responses.

PDNLab represents on-chip grids using a symmetric power-grid abstraction: the supply and return wires are modeled as closely spaced transmission-line pairs, geometrically symmetric so that voltage and current waves on Vdd and Gnd are equal and opposite. That symmetry has two consequences. First, only one rail needs to be solved — the other follows by sign inversion. Second, the magnetic energy is confined to the narrow gap between the two wires, so coupling to nearby signal nets is small and the global RLC behavior of the grid is fully captured by per-unit-length parameters of the pair.

A grid in PDNLab is a G element defined by:

• Sheet resistance (Ω/sq) — sheet R of the metal layer
• Inductance per length (H/cm) — per-unit-length L of the supply/return pair
• Capacitance per area (F/cm²) — per-unit-area C in regions without an explicit decap block
• Wire width (cm) — supply/return wire width
• Wire spacing (cm) — center-to-center pair spacing

For the H100 SM model the CORE grid uses process-level estimates derived from public information about the TSMC 5 nm family:

The CORE grid sits over a single SM (~3.39 mm²). Below M7, the dense via array down to M1 makes the vertical R from a power tap to the transistors on the order of tens of nΩ, so the standard-cell layer can be treated as a uniform tap surface beneath the semi-global grid.

The 36 current sources from the previous section each tap into the CORE grid at the centroid of their block. The grid itself, parameterized as above, then determines how each source’s current waveform translates into a propagating voltage wave on Vdd — the droop map PDNLab solves for.

On top of the per-area background capacitance, we add a single lumped on-die decoupling capacitance region covering the full 1.84 mm × 1.84 mm SM footprint, with a total capacitance of 0.2 µF. This represents the distributed MOS decap built into the SM — gate, diffusion, and dedicated decap cells folded into a single spatial region — and gives the local grid a reservoir of charge to draw from before the package-level PDN can respond to a fast load step.

With the floorplan and the 36 current sources defined, the next step is to represent an actual workload by driving each source with a time-domain current waveform. PDNLab accepts a current profile per source — amps as a function of time — because power-grid droop is a transient phenomenon, dominated by the largest cycle-to-cycle changes in current, not the average.

We model a tensor-heavy AI workload: a warpgroup matrix-multiply (WGMMA) burst, the dominant operation in modern transformer training and inference. We consider two scenarios: in Scenario 1 all four sub-cores fire in lockstep; in Scenario 2 they fire in a column-wise staggered order. Both scenarios share the same operating point and the same per-source amplitudes / pulse shapes; they differ only in when each of the four sub-cores starts its burst. The shared simulation parameters are:

• Clock: 690 MHz (H100 published base clock), giving a clock period of 1.45 ns.
• Supply: 0.6 V core rail at this DVFS state.
• Average SM current: 2.43 A — the activation pattern below is shaped so its time-integral over the 5 ns window matches this average.
• Simulation window: 5 ns — about 3.5 clock cycles. Long enough to capture two back-to-back tensor operations and the inter-burst register-file activity between them.

Scenario 1 — Lockstep firing

In Scenario 1 we treat the four sub-cores as a single synchronous unit: every block of a given type (every Tensor Core, every RF bank, every LDST_SFU) enters and exits each phase at exactly the same instant.

The activation pattern

The pattern below is what we drive into PDNLab. Each phase corresponds to which sources are active and at what current level. The phase currents below are sized so the area under the curve over 5 ns integrates to ~12.2 nC — matching the 2.43 A average (~3.52 nC per 1.45 ns cycle).

Scenario 2 — Column-wise temporal excitation (experimental)

Real GPU workloads do not drive all four sub-cores in simultaneous lockstep. In a software-pipelined WGMMA kernel — the dominant execution pattern in transformer training and inference — the SM advances through overlapping stages at all times: while one warpgroup issues a tensor-multiply instruction, another is staging operands from shared memory or waiting for TMA to complete the next tile load. At any given nanosecond, only a spatial subset of the sub-cores draws peak tensor current. This temporally non-uniform activation is not a failure mode; it is the steady-state operating condition of a pipelined GPU SM.

This scenario is a controlled experiment inspired by that behavior. Rather than modelling a specific kernel schedule, we apply a clean column-wise ordering: the two edge sub-cores (SC0 and SC3, at the left and right of the sub-core row) fire their full tensor burst in Phase C (0.40–1.45 ns); the two center sub-cores (SC1 and SC2) fire in Phase E (3.00–4.35 ns). The edge-then-center sequence is chosen because the two groups occupy distinct impedance environments — edge taps have grid on one side only, while center taps see supply symmetrically on both sides — making the contrast between the two bursts physically informative. This is not a claim that real kernels schedule in exactly this spatial order; it is a deliberate probe of how residual noise left by the first burst alters the droop seen by the second.

Activation pattern

All six phases, amplitudes, and pulse shapes from Scenario 1 are reused verbatim. The only change is which Tensor Cores carry burst current in Phases C and E. All RF banks, sched_dispatch, and SM-shared blocks (L1_ICACHE, SMEM_L1D, TEX, TMA) fire identically in both scenarios — even idle sub-cores maintain quiescent register-file reads for warp scheduling and dependency tracking. The table below shows only the Tensor Core dimension, where the split occurs.

What this reveals about the power grid

If droop were a purely local, memoryless property of the grid, both scenarios would produce the same peak droop — the SM draws the same total current at the same instants. Three effects break that symmetry, and this experiment is designed to make each one visible:

• The grid has memory. The L·di/dt response from the edge-column burst does not vanish by the time the center-column burst starts. Residual ringing and charge displacement on the CORE grid bias the second burst’s droop measurement — the second burst lands on a grid that is already moving.
• Spatial position changes local impedance. Edge taps can only spread current inward; center taps have grid on both sides. Edge-first vs center-first therefore produces measurably different peak droops even with identical SM-level currents at each instant.
• Concentrating current in fewer tiles raises local di/dt density. Two Tensor Cores drawing 1.8 A each pack the SM’s 3.6 A into half the area of four Tensor Cores at 0.9 A each. The grid response per unit area climbs accordingly.

Same model, same total work, deliberately different spatial allocation — and the droop map that comes back tells us how much of the observed swing was a property of where compute landed on the die.

Current profile shapes

The activation pattern fixes which sources are active in each phase and at what amplitude. It does not fix the shape of each pulse: the time-domain function i(t) that a source emits inside its active window. Shape matters because the power grid responds to L · di/dt, not to peak current alone — two sources with the same peak and the same average can produce very different droop if one slews five times faster than the other. We therefore bind every block-type to a pulse shape whose envelope matches the known physical character of the activity in that block.

The full assignment, with the physical justification for each choice:

These are physically motivated engineering defaults, not measurements. Nobody outside NVIDIA® has published per-block current waveforms for an H100 SM. What is defensible is that each shape captures the qualitative envelope of activity in that block — the spectral character (broadband vs narrowband, hard edges vs smooth) is right, which is what matters for the L·di/dt droop response.

Per-source current profiles

The activation pattern (which sources are active per phase) and the pulse shape (per block-type) together define each source’s complete current waveform i(t). To make the math concrete: each source carries a mean current during a phase — its time-average over the phase duration — and the pulse shape modulates the instantaneous current around that mean, normalized so the time-integral over the phase equals mean × phase duration. The mean sets the phase’s charge contribution; the shape sets the di/dt spectrum.

The table below collects everything that defines the SM’s 5 ns activation in one place. Rows are sources, columns are the six workload phases defined earlier (Instruction issue → Wind-down), and every body cell is a mean current in amperes for that source during that phase. Three footer rows summarize each phase: the column sum Σ I_SM (A), the phase duration (ns), and the resulting phase charge Q = Σ I_SM × duration (nC). Blank body cells are at leakage (0.005 A); the “×n” annotation indicates the source has n sub-core instances, each carrying the listed current. The Total column rolls the row up over the full 5 ns window.

The Tensor burst #1 column spreads 4.0 A across the SM as 4 × 0.900 A on the Tensor Cores plus 8 × 0.050 A on the register-file banks; the same shape repeats in Tensor burst #2. The Operand fetch phase’s 1.5 A is dominated by SMEM/L1D (0.86 A) with 0.08 A per RF bank as operands stream in. Convolving these per-phase means with their pulse shapes (Fig. 4) and summing across all 36 sources yields the SM-total current waveform i(t) — the same trace PDNLab later integrates against the power-grid impedance to produce the droop surface in Fig. 6.

The integrated charge of 12.405 nC over the 5 ns window sits within 2.1% of the 12.15 nC budget set by the 2.43 A average derived earlier — well inside the engineering tolerance of the underlying TDP estimate. The activation pattern therefore reproduces the target time-averaged SM current without further tuning.

Based on the defined specifications, we leverage PDNArchitect, a built-in AI Assistant for PDNLab, to generate the model and then to drive it with a workload. We split the work into two prompts: a model prompt that defines the physical SM (floorplan, blocks, power grid) and a workload prompt that defines what the SM is doing (operating point, per-block current profiles, simulation request).

Build a PDNLab model of one NVIDIA® H100 SM. Each block listed
below is a single current source.

# 1. Floorplan (origin at bottom-left, units = mm)
SM die area = 1.840 mm x 1.840 mm = 3.386 mm^2.

Reference diagram (not to scale; +y is up, +x is right;
h = block height in mm):

   y=1.840 +-----------------------------------------+
           |              L1_ICACHE                  |  h=0.060
   y=1.780 +-----------+-----------+-----------+-----+
           | sched_d.  | sched_d.  | sched_d.  | s.. |  h=0.080
           +-----------+-----------+-----------+-----+
           |  RF_bank0 |  RF_bank0 |  RF_bank0 | R.. |  h=0.225
           +-----------+-----------+-----------+-----+
           |   FP32    |   FP32    |   FP32    | F.. |  h=0.088
           +-----------+-----------+-----------+-----+
           |   INT32   |   INT32   |   INT32   | I.. |  h=0.088
           +-----------+-----------+-----------+-----+
           |  RF_bank1 |  RF_bank1 |  RF_bank1 | R.. |  h=0.225
           +-----------+-----------+-----------+-----+
           |   FP64    |   FP64    |   FP64    | F.. |  h=0.151
           +-----------+-----------+-----------+-----+
           |  TENSOR   |  TENSOR   |  TENSOR   | T.. |  h=0.328
           +-----------+-----------+-----------+-----+
           | LDST_SFU  | LDST_SFU  | LDST_SFU  | L.. |  h=0.115
   y=0.480 +-----------+-----------+-----------+-----+
           |              SMEM_L1D                   |  h=0.390
   y=0.090 +-----------------------------+-----------+
           |             TEX             |    TMA    |  h=0.090
   y=0.000 +-----------------------------+-----------+
         x=0.000   0.460     0.920     1.380     1.840
            ^ SC0      ^ SC1      ^ SC2      ^ SC3
         (each sub-core column is 0.460 mm wide)

SM-level stripes (each spans the full width unless noted):
  L1_ICACHE   : x=0.000..1.840, y=1.780..1.840   (h=0.060)
  SUBCORE_ROW : x=0.000..1.840, y=0.480..1.780   (h=1.300)
  SMEM_L1D    : x=0.000..1.840, y=0.090..0.480   (h=0.390)
  TEX         : x=0.000..1.460, y=0.000..0.090   (h=0.090)
  TMA         : x=1.460..1.840, y=0.000..0.090   (h=0.090)

The sub-core row contains four sub-core columns SC0..SC3,
each 0.460 mm wide, at:
  SC0 : x=0.000..0.460
  SC1 : x=0.460..0.920
  SC2 : x=0.920..1.380
  SC3 : x=1.380..1.840

Within each sub-core column SCk, stack 8 sub-blocks
top-to-bottom (top adjacent to I-cache, bottom adjacent to
SMEM). Each sub-block spans the full column width
(x = column x_lo .. x_hi). Explicit y-bands:

  sched_dispatch_SCk : y=1.700..1.780   (h=0.080)
  RF_bank0_SCk       : y=1.475..1.700   (h=0.225)
  FP32_SCk           : y=1.387..1.475   (h=0.088)
  INT32_SCk          : y=1.299..1.387   (h=0.088)
  RF_bank1_SCk       : y=1.074..1.299   (h=0.225)
  FP64_SCk           : y=0.923..1.074   (h=0.151)
  TENSOR_SCk         : y=0.595..0.923   (h=0.328)
  LDST_SFU_SCk       : y=0.480..0.595   (h=0.115)

Naming convention: sub-core instances are suffixed _SC0,
_SC1, _SC2, _SC3 (e.g. TENSOR_SC0, RF_bank0_SC2). SM-shared
blocks (L1_ICACHE, SMEM_L1D, TEX, TMA) have no suffix.

Total = 4 sub-cores x 8 + 4 SM-shared = 36 blocks.

# 2. Power grid
Build a single CORE semi-global M7/M8 grid covering the full SM
(bbox = (0.000, 0.000) .. (1.840, 1.840) mm). Use the G element:
  sheet_resistance     = 0.30 ohm/sq
  inductance           = 5e-9 H/cm
  default_cap          = 1.5e-9 F/cm^2
  wire_width           = 1e-4  cm   (1 um)
  wire_spacing         = 1e-3  cm   (10 um pair pitch)

Drive the existing H100 SM model with a tensor-heavy AI
workload scenario. Name it HGEMM_lockstep (Scenario 1).

# 1. Workload specs / Operating point
Vdd        = 0.6 V
Frequency  = 690 MHz   (clock period = 1.4493 ns)
Window     = 0..5 ns
Avg I_SM   = 2.43 A    (total Q over 5 ns = 12.15 nC)

# 2. Notation
SCk         = a sub-core index, k in {0,1,2,3}.
"X_SCk"     = the four instances X_SC0, X_SC1, X_SC2, X_SC3.
SM-shared sources (L1_ICACHE, SMEM_L1D, TEX, TMA) have no
suffix.

Any source not named in a given phase sits at leakage
= 0.005 A for the duration of that phase.

# 3. Phase amplitudes
The 5 ns window is divided into 6 phases. Each phase lists
named sources with explicit per-source currents in amps (no
weights, no normalization -- the numbers below ARE the
amplitudes each source carries during that phase):

Phase A  0.00..0.20 ns   "Instruction issue"   target I_SM = 0.5 A
   sched_dispatch_SCk : 0.025 A each   (4 sources)
   L1_ICACHE          : 0.400 A
   Sum: 4 x 0.025 + 0.400 = 0.500 A

Phase B  0.20..0.40 ns   "Operand fetch"       target I_SM = 1.5 A
   RF_bank0_SCk       : 0.080 A each   (4 sources)
   RF_bank1_SCk       : 0.080 A each   (4 sources)
   SMEM_L1D           : 0.860 A
   Sum: 8 x 0.080 + 0.860 = 1.500 A

Phase C  0.40..1.45 ns   "Tensor burst #1"     target I_SM = 4.0 A
   TENSOR_SCk         : 0.900 A each   (4 sources)
   RF_bank0_SCk       : 0.050 A each   (4 sources)
   RF_bank1_SCk       : 0.050 A each   (4 sources)
   Sum: 4 x 0.900 + 8 x 0.050 = 4.000 A

Phase D  1.45..3.00 ns   "Accumulation"        target I_SM = 1.3 A
   TENSOR_SCk         : 0.150 A each
   RF_bank0_SCk       : 0.050 A each
   RF_bank1_SCk       : 0.050 A each
   LDST_SFU_SCk       : 0.075 A each
   Sum: 4 x (0.150 + 0.050 + 0.050 + 0.075) = 1.300 A

Phase E  3.00..4.35 ns   "Tensor burst #2"     target I_SM = 4.0 A
   (same per-source amplitudes as Phase C)

Phase F  4.35..5.00 ns   "Wind-down"           target I_SM = 0.6 A
   LDST_SFU_SCk       : 0.100 A each
   SMEM_L1D           : 0.200 A
   Sum: 4 x 0.100 + 0.200 = 0.600 A

# 4. Per-source pulse shape
Within each phase the per-source amplitude listed above is
the source's *mean* current over the phase. The instantaneous
current i(t) follows a fixed block-type pulse shape over
W = phase duration, normalized so the area under the shape
equals (amplitude x W). Peak current is shape-dependent:
~2.40x for Gaussian (sigma=W/6), 2x for raised-cosine,
2x for triangular, 1x for constant.

  TENSOR_SCk     : Gaussian, sigma = W/6
                   (smooth ramp-up, smooth decay)
  RF_bank0_SCk,
  RF_bank1_SCk   : Raised-cosine over W, peak time shifted
                   50 ps earlier than the same-sub-core
                   TENSOR_SCk peak (RF leads its own
                   sub-core's TENSOR by 50 ps)
  LDST_SFU_SCk   : Triangular over W
  SMEM_L1D       : Triangular over W
  All others
  (sched_dispatch_SCk, L1_ICACHE)
                 : Constant at the amplitude for the full
                   phase duration

# 5. Phase transitions
Between adjacent phases, splice the per-source waveforms with
a 100 ps linear ramp centered on the phase boundary (50 ps
into each adjacent phase) so each source's current is
continuous. The 50 ps RF lead in Phase C and E is computed
relative to the TENSOR peak within the same phase; it does
not push the RF waveform across the phase boundary.

# 6. Sanity check
Sum all 36 source currents at every time step and integrate
over 0..5 ns. The total charge must equal 12.15 nC +/- 2%.

Drive the existing H100 SM model with a tensor-heavy AI
workload scenario. Name it HGEMM_colwise (Scenario 2).

This scenario is identical to Scenario 1 (HGEMM_lockstep) in
every respect EXCEPT the spatial distribution of Tensor Core
firing during Phases C and E. The intent is a controlled
A/B comparison against Scenario 1: same model, same six
phases, same per-phase SM-total currents, same pulse shapes
and phase-transition rules, same operating point, same
sanity-check target. The only knob being changed is WHICH
TENSOR_SCk sources carry the burst current in Phases C and E.

# 1. Workload specs / Operating point  (unchanged from Scenario 1)
Vdd        = 0.6 V
Frequency  = 690 MHz   (clock period = 1.4493 ns)
Window     = 0..5 ns
Avg I_SM   = 2.43 A    (total Q over 5 ns = 12.15 nC)

# 2. Notation  (unchanged from Scenario 1)
SCk         = a sub-core index, k in {0,1,2,3}.
"X_SCk"     = the four instances X_SC0, X_SC1, X_SC2, X_SC3.
SM-shared sources (L1_ICACHE, SMEM_L1D, TEX, TMA) have no
suffix.

Sub-core spatial layout (left-to-right across the SM):
   SC0      SC1      SC2      SC3
  (edge)  (center) (center)  (edge)

  EDGE   group = {SC0, SC3}
  CENTER group = {SC1, SC2}

Any source not named in a given phase sits at leakage
= 0.005 A for the duration of that phase.

# 3. Phase amplitudes
Phases A, B, D, F are IDENTICAL to Scenario 1. Only Phases C
and E are redefined. Phase D ("Accumulation") still drives
all four TENSOR_SCk at 0.150 A each, as in Scenario 1 -- the
post-burst accumulation tail is shared by all four sub-cores
regardless of which fired the preceding burst.

Phase A  0.00..0.20 ns   "Instruction issue"   target I_SM = 0.5 A
   sched_dispatch_SCk : 0.025 A each   (4 sources)
   L1_ICACHE          : 0.400 A
   Sum: 4 x 0.025 + 0.400 = 0.500 A

Phase B  0.20..0.40 ns   "Operand fetch"       target I_SM = 1.5 A
   RF_bank0_SCk       : 0.080 A each   (4 sources)
   RF_bank1_SCk       : 0.080 A each   (4 sources)
   SMEM_L1D           : 0.860 A
   Sum: 8 x 0.080 + 0.860 = 1.500 A

Phase C  0.40..1.45 ns   "Tensor burst #1 (EDGE)"
                                          target I_SM = 4.0 A
   TENSOR_SC0, TENSOR_SC3 : 1.800 A each (2 sources, EDGE)
   TENSOR_SC1, TENSOR_SC2 : leakage 0.005 A each (CENTER idle)
   RF_bank0_SCk           : 0.050 A each (all 4 sub-cores)
   RF_bank1_SCk           : 0.050 A each (all 4 sub-cores)
   Sum: 2 x 1.800 + 2 x 0.005 + 8 x 0.050 = 4.010 A
   (~0.25% above 4.0 A target due to held leakage; acceptable)

Phase D  1.45..3.00 ns   "Accumulation"        target I_SM = 1.3 A
   TENSOR_SCk         : 0.150 A each   (all 4 sub-cores)
   RF_bank0_SCk       : 0.050 A each
   RF_bank1_SCk       : 0.050 A each
   LDST_SFU_SCk       : 0.075 A each
   Sum: 4 x (0.150 + 0.050 + 0.050 + 0.075) = 1.300 A

Phase E  3.00..4.35 ns   "Tensor burst #2 (CENTER)"
                                          target I_SM = 4.0 A
   TENSOR_SC1, TENSOR_SC2 : 1.800 A each (2 sources, CENTER)
   TENSOR_SC0, TENSOR_SC3 : leakage 0.005 A each (EDGE idle)
   RF_bank0_SCk           : 0.050 A each (all 4 sub-cores)
   RF_bank1_SCk           : 0.050 A each (all 4 sub-cores)
   Sum: 2 x 1.800 + 2 x 0.005 + 8 x 0.050 = 4.010 A

Phase F  4.35..5.00 ns   "Wind-down"           target I_SM = 0.6 A
   LDST_SFU_SCk       : 0.100 A each
   SMEM_L1D           : 0.200 A
   Sum: 4 x 0.100 + 0.200 = 0.600 A

Rationale for the 0.900 -> 1.800 A doubling: holding the
SM-total burst current at 4.0 A while reducing the count of
active TENSOR_SCk sources from 4 to 2 requires the per-source
amplitude to double. This packs the same SM-level current
into half the die area during each burst -- the central
physical question of the experiment.

# 4. Per-source pulse shape  (unchanged from Scenario 1)
Within each phase the per-source amplitude listed above is
the source's *mean* current over the phase. The instantaneous
current i(t) follows a fixed block-type pulse shape over
W = phase duration, normalized so the area under the shape
equals (amplitude x W). Peak current is shape-dependent:
~2.40x for Gaussian (sigma=W/6), 2x for raised-cosine,
2x for triangular, 1x for constant.

  TENSOR_SCk     : Gaussian, sigma = W/6
                   (applies to whichever 2 sub-cores are
                    active in the phase; leakage sub-cores
                    hold their 0.005 A flat)
  RF_bank0_SCk,
  RF_bank1_SCk   : Raised-cosine over W, peak time shifted
                   50 ps earlier than the same-sub-core
                   TENSOR_SCk peak in Phases C and E. For
                   sub-cores at leakage in that phase, the
                   RF lead is referenced to the phase-center
                   time (no shift).
  LDST_SFU_SCk   : Triangular over W
  SMEM_L1D       : Triangular over W
  All others
  (sched_dispatch_SCk, L1_ICACHE)
                 : Constant at the amplitude for the full
                   phase duration

# 5. Phase transitions  (unchanged from Scenario 1)
Between adjacent phases, splice the per-source waveforms with
a 100 ps linear ramp centered on the phase boundary (50 ps
into each adjacent phase) so each source's current is
continuous. For TENSOR_SCk sources transitioning between
"active" and "leakage" across a phase boundary (e.g. SC0
going from 1.800 A peak in Phase C tail down to 0.150 A in
Phase D, or SC1 ramping from 0.150 A in Phase D up to
1.800 A peak in Phase E), the same 100 ps splice rule
applies -- no discontinuities at phase boundaries.

# 6. Sanity check
Sum all 36 source currents at every time step and integrate
over 0..5 ns. The total charge must equal 12.15 nC +/- 2%
(same target as Scenario 1, since SM-total current per phase
is unchanged).

# 7. Required output for A/B comparison with Scenario 1
- Per-source current waveforms i_k(t) for all 36 sources.
- SM-total current I_SM(t).
- Time-resolved Vdd droop map over the SM floorplan at
  matching timesteps to the Scenario 1 run (recommend 25 ps
  sampling, identical to Scenario 1) so the two droop maps
  can be diff'd frame-by-frame.
- Report peak local droop, time of peak, and (x, y) tile of
  peak for each of Phase C and Phase E separately.

We run the HGEMM workload twice against the same SM netlist — once with the four sub-cores firing in lockstep (Scenario 1) and once with the column-wise temporal excitation — edge sub-cores first, center sub-cores second — (Scenario 2). PDNLab solves for the time-resolved Vdd droop across both the SM’s semi-global grid and the die-wide global grid in both cases. The animations below replay the full 5 ns window as a height map of the local supply voltage: peaks are regions briefly above nominal (supply bounce), valleys are local droop.

Scenario 1 — Lockstep firing

(a) Semi-global grid (M7/M8) under the SM — the surface the four Tensor Cores see directly.

(b) Die-wide global grid (M14/M15) — how the transient propagates up through the 36 semi-global-to-global vias and out into the package-facing rail.

The two tensor bursts dominate the response: the entire CORE grid plunges in concert as four Tensor Cores draw ~4 A together, and the on-die decap visibly redistributes charge between bursts. The operand-fetch and accumulation phases produce smaller, broader perturbations that ride on the residual ringing of the prior burst. This is the curve a sign-off team would use to set decap budget under the conservative “all-at-once” assumption.

Scenario 2 — Column-wise temporal excitation

(a) Semi-global / core view — outer slices then inner slices.

(b) Die-wide / global view — how the column-wise excitation propagates.

The first burst lights up the left and right edges of the sub-core row, producing two distinct droop wells with grid between them that ringingly recovers as the burst ends. By the time the second burst starts at 3.00 ns, the on-die decoupling has not fully damped the residual swing from burst #1 — the inner-slice burst therefore lands on a grid that is still oscillating around nominal. The droop excursion at the inner Tensor Cores (SC1, SC2) reaches a peak that is slightly deeper than the outer-slice peak even though both bursts deliver the same SM-total current, because the residual ringing from burst #1 adds (constructively, in this ordering) to the new inductive transient. Concentrating the 3.6 A burst into two adjacent Tensor Cores rather than four also raises the local current density, which is visible as a sharper, narrower well in the droop map versus Scenario 1’s broader basin.

Side-by-side comparison

Both scenarios deliver the same total charge and the same SM-total peak current per burst. What changes is the spatial allocation of that current within each burst — and that change alone is enough to move the per-burst peak droop by ~10–15% and to break the symmetry between burst #1 and burst #2 (which were identical in Scenario 1 by construction). The fact that the inner-slice burst, which lands on a still-ringing grid, droops deeper than the outer-slice burst quantifies the residual-noise effect that Scenario 2 was designed to expose.

As seen from the two workload scenarios explored, changes in a Functional Unit workload sequence produce significant changes in cumulative voltage droop. PDNLab explores such scenarios and helps choose the activation sequence that permits the lowest operating voltage — a key determinant for optimizing static and dynamic power consumption.

Designers, often burdened with the knowledge that interconnect power has surpassed transistor device power, attempt to minimize interconnect lengths thereby creating compact floor plans. Such floor plans may be estimated by other EDA tools as lower in power but are often much degraded in power integrity. PDNLab reveals the PI consequences of such overly compact and congested functional units.

Power consumption depends quadratically upon the operating voltage that switching circuits employ. A simple thought experiment (a Gedankenexperiment, Albert Einstein's favorite!) helps shed more light here: interconnect power is proportional to C_line · V² f + I² · R_line, and if line length is doubled while voltage is reduced by a factor of 1/√2, power consumed in both the capacitive and resistive aspects remains the same (assuming I varies linearly with V in nanoscale devices). Interconnect delay also doubles (C_line · V / I, RC_gate) and critical path timing will need careful optimization, but power consumed in the transistor device capacitance of the entire functional unit is reduced to half (1/2) its previous value — which likely will help reduce overall power consumption significantly. While this scenario described is entirely hypothetical, its conceivable that a floor plan optimized for power integrity could allow the lowest possible operating voltage, and despite longer interconnect lengths, could also result in lower functional unit power and energy consumption.

Cramming more circuit components in lesser and lesser area (or 3D volume) is not necessarily an improvement from power, heat, and noise perspectives!