Planning the Power Delivery Network of an AI Accelerator

Ask how the power delivery network of an AI accelerator gets designed, and the honest answer is that almost none of it begins with the grid. It begins with a map of where power is spent and how quickly that spending changes, a partition of the die into voltage domains, and a budget for how far the supply is allowed to move at each point in the stack. The grid itself — the widths, the pitches, the layers, the bump patterns — is what falls out of those decisions, not what drives them. A modern accelerator makes this unusually stark, because it is not a uniform sea of logic but a heterogeneous system: replicated compute tiles, large memory interfaces, an on-die network, and high-speed I/O, each with its own power density, its own transient signature, and often its own supply rail. Planning its PDN is the discipline of reading that heterogeneity correctly and then hardening the supply against the one thing accelerators do that few other chips do — switch enormous amounts of logic in near-perfect unison. This article is about how that thinking actually proceeds, decision by decision.

1 · It starts with a power map, not a grid

The first artifact of power planning is not a grid but an annotated floorplan: every major block placed, and each labeled with how much current it will draw and how fast. This matters because an accelerator is deeply non-uniform in both quantities. The compute tiles that run matrix math dissipate several times the power density of the cache that feeds them, and they do it with far steeper current transients. Designing a single uniform grid to a chip-average number would simultaneously over-build the quiet regions — wasting metal and routing tracks the signal router desperately needs — and under-build the hotspots, where the supply would collapse under load. So the map, not a rule of thumb, is what tells the engineer where to concentrate metal, capacitance, and bumps.

Reading the map means understanding that each class of block presents a different power-delivery problem:

2 · Partition the die into voltage domains

Before the grid takes shape, the architecture decides how many independent supplies the die needs, and where their boundaries fall. This is one of the highest-leverage decisions in the whole plan, because each voltage domain is effectively its own PDN: its own grid, its own isolation from neighbors, its own decoupling, level shifters at every crossing, and frequently its own regulator phase off-chip. A modern accelerator typically carries a compute-core rail that scales with dynamic voltage-frequency management, one or more memory rails for the HBM interface, a quiet analog rail for the high-speed links, and an always-on rail that keeps management logic and state alive while the rest of the chip power-gates.

The engineering judgment is about granularity. Finer domains — per-cluster or even per-tile voltage and frequency control — save energy and let the chip push hot tiles harder while idling cold ones, but each boundary adds level shifters, isolation cells, complexity in the grid, and another rail to regulate and decouple. Coarser domains are simpler and cheaper to deliver power to but leave energy on the table. The chosen partition, expressed as power intent in UPF or CPF, then dictates how many grids the plan replicates and where the isolation seams run. Every later grid decision inherits this partition, so it is made first and deliberately.

3 · Budget the impedance across the whole stack

The supply that reaches a transistor has travelled through the voltage regulator, the board, the package, and the on-die grid, and no single one of those tiers can hold the rail steady across all frequencies. Each is effective only over a band. The regulator and its bulk capacitors respond over microseconds and slower, covering the low-frequency envelope of a workload ramp. The package — its planes and its mounted capacitors — covers the middle band. The on-die decoupling capacitance and the grid itself own the highest frequencies, the fast transients that the package’s series inductance simply cannot service in time. Power planning therefore begins with a target impedance for the rail and allocates it across these tiers: how much of the allowed droop each tier is responsible for absorbing, and how much decoupling capacitance of each class that requires.

4 · The defining problem: coherent di/dt

Everything to this point is common to any large chip. What sets an accelerator apart, and what dominates its PDN planning, is the structure of its activity. AI compute is deliberately synchronous and massively parallel: a matrix multiply drives every lane of every tensor engine on the same cycles; a kernel launch wakes a clock-gated array of cores in a single step; a synchronization barrier idles them together. The current these blocks draw is therefore not the statistically-smoothed switching of random logic, where thousands of uncorrelated gates average out. It is coherent — tens or hundreds of amperes stepping up or down within a few clock cycles, aligned across large regions of the die at once.

Coherent steps are the worst possible excitation for a power grid. A sharp, correlated current transition carries strong spectral energy right at the package–die resonance, so it drives the supply into its deepest ring rather than a gentle sag. This is why, for an accelerator, average power tells you almost nothing about the hardest case: two workloads with identical average dissipation can produce completely different droop depending on how synchronized their switching is. The design target is the coherent worst case — the moment the whole tensor array turns on together — not the mean.

The mitigations an engineer reaches for follow directly from that picture, and they span the grid, the capacitance, and the clock:

5 · Exploit the tiling

The feature that makes an accelerator hard — thousands of identical compute lanes — is also the planner’s single greatest lever. Because the compute fabric is an array of near-identical tiles, the PDN does not have to be solved uniquely everywhere. The engineer designs a per-tile power template — the local grid pitch and width, the in-tile decoupling, the bump sub-array, and the taps that connect the tile up to the global grid — and verifies that one template against the worst-case coherent load a single tile can produce. Once a tile is right, it is replicated across the array, and a coarser global grid stitches the tiles together and handles die-scale redistribution between them.

This decomposition is what makes a full-chip problem tractable: solve one representative tile well, solve the handful of genuinely unique blocks — the HBM PHY, the SerDes, the large shared cache, the network fabric — each with a bespoke grid matched to its character, and then solve the global stitch that ties them into one network. The regularity that produces the coherent-di/dt problem in the first place is the same regularity that lets the plan be built and verified without treating every square micron as unique.

6 · Tailor the grid region by region — and win the congestion fight

The consequence of designing to a power map is that the finished grid is not uniform. It is dense over the compute hotspots, lighter over the cache, and deliberately isolated and quiet around the analog links. That non-uniformity is where the hardest routing conflict of the whole floorplan lives, and it is not incidental: the very blocks that need the most power-ground metal — the tensor tiles — are also the blocks that need the most signal routing, so the grid and the router compete for the same tracks exactly where the pressure is highest.

Resolving the conflict is a set of concrete moves: assigning the heavy power straps to the thick upper metals where they do not compete with dense local signal routing, connecting them down with via pillars, offsetting adjacent layers to control coupling, placing PG blockages where a region cannot spare the tracks, and — when routability and the frequency target genuinely collide — trading a little of one for the other. Each region ends up with its own pitch, width, layer assignment, and bump density, all traceable back to what the power map said it would demand.

7 · Co-design the bumps and the package

It is easy to treat the on-die grid as the whole problem, but on a high-current accelerator the real bottleneck is often how current gets onto the die at all. Current enters through an array of flip-chip bumps, and there are only so many of them; the ratio of power to ground bumps, and where those bumps sit relative to the hotspots, determines whether current is injected where it is actually demanded or has to spread laterally across resistive metal to get there. Aligning the power-bump field over the coherent-switching tiles is as much a part of the plan as the stripes themselves, and it forces power planning and package design to proceed together rather than in sequence.

The package sets the terms for the dynamic problem, too. Its series inductance, together with the on-die capacitance, fixes the frequency of the package–die resonance that the coherent di/dt excites — so package and on-die decoupling are sized against each other, not independently. Modern accelerators push this further: many are multi-die, with compute chiplets and HBM stacks mounted on a silicon interposer, and the PDN then has to share and balance current across dies through the interposer and the bonds between them. And the emerging shift to backside power delivery — routing the supply from the wafer’s back side — shortens the vertical path and frees front-side tracks for signals, changing the planning calculus again, while removing resistive damping in a way that makes the dynamic droop the earlier sections describe more pronounced, not less.

8 · How the decision actually converges

All of these decisions have to be made in a specific and awkward order, because the information needed to make them well does not exist yet when they must be made. Accurate current density requires knowing where cells are placed; placement, in turn, has to work around a grid that must already exist. The plan resolves this circularity by iterating from estimates. The engineer starts from an estimated power map and a prototype grid template, runs an early dynamic analysis — vectorless, or driven by representative workload activity — finds the regions that droop, over-heat, or violate electromigration, and fixes them by widening straps, adding decoupling, adding bumps, re-striping, shaping activity, or moving a block. Then the loop repeats, and the plan is frozen early — because by the time sign-off runs its full static and dynamic checks, the floorplan is fixed and the expensive decisions are already locked in.

The uncomfortable truth in that ordering is that the decisions with the largest consequences — domain partition, tile template, bump and package co-design, where the hotspots sit — are made earliest, on the least information. That is precisely why the ability to evaluate full-chip dynamic behavior at floorplan stage, quickly enough to run inside the iteration loop, is so valuable: it lets an engineer see the coherent-di/dt response of a candidate plan while a block can still be moved, a rail still added, or a tile still re-templated — rather than discovering the droop at sign-off, when the only remaining option is to slow the chip down. Fast, physically-accurate dynamic simulation is what turns power planning from a static-margin exercise into a design of the transient itself.