This paper makes a clean, important claim: LLM inference doesn’t just draw a lot of power — it draws it in a rhythm, and when that rhythm lands on a GPU’s power-delivery resonance, the voltage droop is amplified far beyond what the raw power swing would predict. It is the first systematic study of LLM–PDN resonance, and its headline number is the kind that reorders priorities: at resonance, a 10 W power swing produced a larger droop than a 100 W swing off-resonance. Here is a walkthrough of what they did, the physics underneath it, and where it fits.
The claim, and why it matters
Traditional reliability analysis worries about a workload’s peak power. The paper’s insight is that for LLMs the more dangerous property is the frequency content of the power. LLM inference is highly structured and repetitive: the nested-loop GEMMs that dominate transformer attention alternate between high- and low-intensity phases, producing periodic power oscillations in the MHz range. Profiling real models (Gemma3 and DeepSeek-R1) on hardware, the authors find most of these oscillations sit in the 10–30 MHz band — precisely where typical GPU PDN resonances live. When the two align, droop is amplified through constructive interference, and the result can cross the supply noise margin and threaten silent data corruption.
What resonance is
In general terms, resonance is the frequency at which a system naturally wants to oscillate, where it responds to a periodic push with the largest amplitude. The everyday picture is a child’s swing: push it at its natural rhythm and small pushes build into huge arcs, because each push arrives in phase with the motion; push at the wrong rhythm and almost nothing happens.
A power delivery network has the same behavior because its inductance (L) and capacitance (C) form an L–C tank. The paper defines the resonant frequency as the point where inductive and capacitive reactance cancel:
At that frequency the PDN’s impedance Z(ω) spikes to a peak — the network’s inability to respond quickly to a current demand. Since droop is voltage = current × impedance,
a current that oscillates near f0 sees a huge impedance and produces a large voltage swing — and because each cycle arrives in phase, the droop builds up over a few cycles. Off-resonance the impedance is low, so even a big current swing makes only a small droop. That is the entire mechanism the paper exploits: resonance turns a small, well-timed power oscillation into a large droop.
Their GPU PDN model
The authors model the GPU power delivery network as a lumped ladder RLC network — the classic board-to-die equivalent circuit — with cascaded R–L–C segments for each physical tier:
| Aspect | What they did |
|---|---|
| Topology | Cascaded RLC ladder capturing PCB traces, package interconnect, bumps, and the die, terminating in a single load node. |
| Component values | Milliohm-scale resistances, inductances from tens of nH at the board down to single-digit pH at the die, and capacitances from µF bulk/on-die down to pF; on-die decoupling capacitance ~1.0–3.8 µF (swept). |
| Calibration | Built from NVIDIA® A100 specifications plus prior PDN studies, then scaled with Leng et al.’s TDP-based technique (~4×, reflecting the A100’s ~400 W vs. a ~55 W Pentium-4 reference). |
| Resonances | The two-tier ladder yields two peaks: 35 MHz (first-droop) and 1.5 MHz (second-droop). |
| Solver | SPICE transient simulation, driven by power profiles measured on real hardware (A100, 40 GB, 1410 MHz) at MHz resolution. |
A forward-looking point falls out of the model: bigger dies carry more on-die capacitance, which (via f0 = 1/2π√(LC)) pushes the resonant frequency downward — toward the 10–30 MHz band the LLMs already occupy. So the dangerous alignment gets worse as silicon scales, not better.
How they profiled the workload
Characterizing the frequency content of an LLM’s power draw is harder than it sounds, and the authors use a two-pronged, multi-granularity approach because no single method can both run real models and resolve MHz oscillations.
- Hardware profiling (real GPU, coarse). They run full inference of two models — Gemma3 27B and DeepSeek-R1 Distill Qwen 32B — on an A100 using NVIDIA’s TensorRT runtime with NVML power monitoring. This captures the envelope: abrupt transitions and swings of 50–150 W. But NVML samples only every ~25 ms (~40 Hz), while the dangerous oscillations are in the MHz range — orders of magnitude faster. Hardware shows that power is unstable, not the frequencies that hit resonance.
- Simulation profiling (the workhorse, fine). To reach MHz resolution they switch to AccelSim (a cycle-level GPU microarchitecture simulator) feeding AccelWattch (its power model), producing a high-resolution power trace. Because A100 power parameters aren’t public, they calibrate GV100 parameters to match A100 hardware — so absolute watts are approximate but the oscillation patterns are representative. The trace then passes through a custom oscillation analyzer using sliding windows of varying width (wide windows detect low frequencies, narrow windows resolve high ones) to extract the periodic components in the MHz band that overlaps PDN resonance.
Drilling to the kernel level reveals where the oscillation comes from. GEMM kernels show a lower-frequency component near 4 MHz — from the nested tile-iteration loops and thread-block scheduling — and a higher one near 29 MHz, from instruction-level pipeline and tensor-core scheduling, right up against the 35 MHz PDN resonance. Attention kernels oscillate near 30 MHz over many cycles; reduction kernels are mild (~2 MHz, low amplitude); elementwise kernels are mixed. The signature is structural — it comes from how transformer inference tiles and schedules on the GPU, not from any one model.
Do all calls look the same?
Largely yes in pattern, but the severity depends on the call — and the paper’s own data shows why:
- Model to model: Gemma3 and DeepSeek-R1 show similar GEMM oscillation frequencies (mostly 10–30 MHz); what differs is the number and amplitude of events per kernel — e.g. DeepSeek-R1’s
020-gemm-3oscillates more than043-gemm-6, driven by GEMM size, loop structure, and tiling, with some amplitudes exceeding 35 W. - Sequence length: no clear monotonic trend — because of tiling, longer sequences decompose into similarly-sized tiles, so the per-tile pattern (and its oscillation) stays comparable. A longer call mostly means more repetitions of the same oscillation, not a different one. This is precisely why calls repeat.
- Batch size: the biggest knob — batch 1 has the highest amplitude (low utilization → more pronounced swings); larger batches raise and steady utilization, smoothing the oscillation.
- DVFS wildcard: clock-frequency changes can shift a kernel’s oscillation onto or off resonance, so the same kernel can be more or less dangerous depending on the clock state at that moment.
Net. The oscillation is a structural, repeatable property of transformer inference — calls of the same model look alike in frequency content. The risk of any given call is set by batch size (smaller is worse), which kernels dominate it, and whether DVFS happens to park the oscillation on the PDN’s resonant frequency.
The key result
The central experiment compares the same PDN driven at a non-resonant frequency versus at its 35 MHz resonance:
- Off-resonance: a large ~100 W power swing produced only 45–80 mV of droop beyond the static baseline.
- At resonance: a mere 10 W swing — ten times smaller — produced droops exceeding 105 mV within just four oscillation cycles.
The takeaway. A 10× smaller power disturbance caused a larger droop purely because it was at resonance. Operating at a resonant frequency produced droops up to 2× larger than conventional workloads, and the stressmark could push droop up to ~28% of supply.
The numbers carry over to real workloads. Traces begin ~80 mV below nominal from static IR drop, with resonant oscillation stacking on top. Across real LLM kernels the authors measured droops from 45–103 mV (Gemma3) and 55–120 mV (DeepSeek-R1), with several kernels exceeding the 100 mV critical threshold — a dangerous ~10% of a sub-volt supply — and their synthetic stressmarks reaching 100–250 mV. To enable this systematically, they also contribute an automated di/dt “stressmark” generator that synthesizes workloads with controllable oscillation frequency and amplitude.
The mitigation: warp-level staggering
Their fix is elegant and software-only. The danger comes from synchronized execution — many warps firing in lockstep concentrate the power pulse at a single frequency. By deliberately un-aligning warp launches with a small per-warp delay, the synchronized pulse is spread in time, which shifts the power-oscillation frequency off resonance. The result: worst-case voltage droop reduced by about 20%, at a runtime overhead of only tens of microseconds (~0.7% of kernel time). It is, in effect, the scheduler-level version of detuning a resonance.
What it establishes — and what it leaves open
The contribution is solid and the lumped RLC ladder is exactly the right instrument for the question they asked: does di/dt-driven resonance happen, and how large is the aggregate droop at the die terminals? The frequency-domain framing nails that, and the 10 W-beats-100 W result is a genuinely useful reframing of the reliability problem — it is the spectrum, not just the magnitude, of a workload that matters.
The model’s scope is also its honest boundary. It terminates in a single load node — there is no spatial resolution of the die. It cannot answer where on the die the instability concentrates, how spatially separated cores (one SM versus another, one GPC versus another) interact, or how a specific kernel’s spatial footprint shapes the droop surface. A lumped model collapses the whole die to one point by construction. Those spatial questions are the complementary half of the picture — the part a distributed, continuum / true-electromagnetic model (such as Anasim’s PI-FP and PDNLab) is built to resolve. The two are consistent, not competing: this paper establishes resonance as a measurable, system-level reliability risk; a spatial model shows where it lands and how to lay out the floorplan, grid, and decap to survive it.
Reviewed from the original: Z. Jiang, J. Garrigus, A. Seigler, E. Syed, Y.-L. Huang, M. Sadi, T. Rahal-Arabi, and L. K. John, “Exploration of LLM Workload Reliability based on di/dt Effects and Voltage Droops,” 2026 IEEE International Symposium on High-Performance Computer Architecture (HPCA), University of Texas at Austin & AMD. Quantities and component ranges are as reported by the authors; figures and exact values appear in the paper.