A PDNLab model can feel like it has a layer of analog magic — change one number and the voltage surface gets quieter or louder for reasons that aren’t obvious. It isn’t magic. The on-chip power grid is a distributed R–L–C system, not a resistor, and every parameter you set is either fixed by your process or genuinely yours to tune. This guide separates the two, explains what each knob physically does, and walks through how an engineer actually decides what to change.
First, the right mental model: the grid is an R–L–C medium
The most common source of confusion is carrying over the intuition that a power grid is a resistor. If it were, design would be simple: lower the resistance and the droop goes down. But a real on-chip grid carries fast current transients, and at those speeds three physical quantities are in play at once:
- Resistance (R) — the conductor’s opposition to steady current. It sets the static IR drop, and — less obviously — it damps the grid.
- Inductance (L) — opposition to changes in current. It is what turns a fast load ramp into a voltage drop:
V = L·di/dt. - Capacitance (C) — stored charge that can be delivered locally and instantly, before the grid’s inductance has time to react.
Put those together and the supply voltage at any point on the die follows, in simplified terms:
The first term is the slow, steady sag. The second is the fast, dynamic spike. But because L and C sit together in the same network, the grid also rings — it has a natural resonance like any L–C circuit, with a frequency and a wave velocity set by how much L and C the structure has:
This is why a PDNLab voltage surface doesn’t just sag under load — it can overshoot, oscillate, and propagate disturbances across the die as a wave. Once you see the grid as an R–L–C medium, every parameter has a clear job, and the “magic” goes away.
What’s fixed by process vs. what you actually tune
In PDNLab, a chip power grid is a G element with seven parameters. The single most useful thing you can do as a modeler is know which of those are handed to you by the foundry and which are real design decisions. Mixing the two up is what makes parameter tuning feel arbitrary.
Parameter (G field) | What it is | Set by | Tunable? | What happens when you change it |
|---|---|---|---|---|
Wire width w |
Width of the power/ground straps | Layout & routing | Yes | Wider straps put more metal down: lower R and L, more area covered → quieter grid, at the cost of routing area. |
Wire spacing s (pitch) |
Pitch between strap pairs | Layout & routing | Yes | Tighter pitch = denser grid = lower effective impedance per unit area → less droop, at the cost of routing tracks. Your primary knob. |
Sheet resistance Rs |
Ω/□ of the chosen metal layer | Process (the metal layer) | Mostly fixed | Sets IR drop and damping. You don’t freely dial this — it’s a property of which layers you route the grid on (see below). |
Inductance L |
Inductance per unit length | Geometry & process | Semi-fixed | The driver of L·di/dt noise. You rarely lower it directly; you fight it with capacitance and grid density. |
Default cap C · explicit C blocks |
Area capacitance (F/cm²) or a lumped decap | Design (decap budget) | Yes | The local charge reservoir. More C → shallower droop, but it also lowers the resonant frequency and its placement matters as much as its amount. |
The short version. You tune grid density (wire width and pitch) and capacitance (how much, and where). You mostly inherit sheet resistance and inductance from the process and the metal stack. Good modeling is spending the two knobs you own well, given the two you don’t.
Grid density: your primary knob
Consider a typical SM-grid setup: a wire width of 10 µm with a pair-to-pair spacing of 100 µm. That sounds dense until you do the arithmetic — only about 20% of the area is covered by metal. The other 80% is gaps. A sparse grid like that has high effective resistance and inductance per unit area, and it will show correspondingly large noise on the voltage surface.
This is the cleanest lever you have. Tighten the spacing from 100 µm to 50 µm, or even 30 µm, and metal coverage climbs from ~20% toward 30–65%. The grid’s impedance drops, and the droop drops with it — often dramatically. Wire width does the same thing from the other direction. Both are concrete, real-world decisions made during the floorplanning and routing of an individual core, which is exactly the stage where PDNLab is meant to inform the design.
The cost, of course, is routing resources: every track you give to the power grid is a track unavailable for signal routing. That tension — grid robustness versus routing congestion — is the real design tradeoff, and PDNLab lets you put numbers on the “robustness” side of it before you commit.
Sheet resistance and damping: the counterintuitive one
Here is the part that trips up almost everyone, and the reason a model can behave the opposite of expectation. Instinct says: lower the resistance, get a better conductor, get less noise. For the static IR term that’s true. For the dynamic behavior it can be exactly backwards.
In any L–C system, resistance is what provides damping — it bleeds energy out of the oscillation so the ringing dies down quickly. Roughly, the damping of the grid scales as:
Drop the sheet resistance to a very low value and you remove damping. An underdamped grid rings harder and longer — so a “more conductive” grid can actually show more transient noise, not less. This is the single most important reason PDNLab results sometimes move in the surprising direction.
Practical note. You usually can’t exploit this even if you wanted to. On a process like TSMC’s 4N, the upper metal layers used for global distribution (M7, M8) have a relatively high sheet resistance, so you can’t lower it dramatically — it’s set by the layer, not by you. The lesson isn’t “make R small” or “make R large” — it’s that R is a real, two-edged parameter, and silently setting it to an unrealistic value will give you a misleading surface.
Capacitance: the local charge reservoir
Inductance resists fast current changes, which means when a core suddenly demands current, the inductive grid can’t supply it instantly — and the voltage collapses. Capacitance is the answer: charge stored right next to the load that can be delivered in the first nanoseconds, before the grid has to respond. In PDNLab, capacitance is associated with the on-chip grid — either baked into the grid as an area capacitance (the G element’s default cap, e.g. 5 µF/cm²) or added explicitly as C blocks over a region.
The question is always how much and where. A useful sanity check: figure out the charge a core needs to ride through a transient, and confirm the model actually has that capacitance associated with it. For an H100-class part, a rough budget is on the order of 10 µF spread across ~144 cores — so each core should carry roughly its share, either as the grid’s 5 µF/cm² area cap or as an explicit decap block. If a core in your model is missing its share of capacitance, it will show artificially deep droop that no amount of grid tuning will fix.
Two cautions make capacitance feel less magical:
- More isn’t free. Adding capacitance lowers droop but also lowers the L–C resonant frequency (
f0 = 1/2π√(LC)) — you can move a resonance into the band your workload actually excites. - Placement beats budget. Capacitance only helps within the frequency band set by the inductance of the loop connecting it to the load. A large reservoir placed far away does little for a fast, local event. Decap near the hot core is worth far more than the same farads parked at the package.
A worked decision: the SM grid shows 30–40 mV
Suppose you build an SM core, run it, and the local grid surface shows 30–40 mV of noise. What do you actually change? The order of operations matters more than any single number:
- 1. Check capacitance first. Confirm the core carries its required area capacitance (the 5 µF/cm² in the grid, or an explicit
Cblock adding up to its share of the ~10 µF ÷ 144 budget). A missing reservoir is the most common cause of artificially deep droop. - 2. Tighten grid density. If coverage is sparse (the 10 µm / 100 µm, ~20% case), reduce the pitch toward 50 or 30 µm. This is the lever with the most headroom and the most realistic design meaning.
- 3. Don’t reach for sheet resistance. Slashing
Rsreduces damping and can make the ringing worse — and on a real process the upper-metal sheet resistance is fixed anyway. - 4. Know when to stop. Because we don’t know the exact tradeoffs the real chip’s designers made, a largish 30–40 mV on the SM grids is acceptable given the approximate nature of an externally-built model. The goal is relative insight and hotspot location — not a sign-off number.
And there is a hierarchy worth remembering: the global grid’s noise only becomes significant if the local SM-core grid noise is already significant. Get the local cores right first; the global picture follows.
The modeling mindset
The throughline of all of this: a PDNLab model is a physical instrument, not an oracle. You set parameters that correspond to real layout and process choices, the solver tells you how the R–L–C grid actually behaves, and your job is to interpret the surface and decide which of the knobs you genuinely own — density and capacitance — to spend. When a result surprises you, it’s almost always one of the effects above: a missing decap reservoir, a sparse grid, or damping moving the opposite way from intuition.
These are the practical design considerations that live at the floorplanning and routing stage of an individual core — which is precisely the window where shifting power-integrity analysis left, into PDNLab, changes the outcome while the grid is still yours to shape.