On-chip power distribution went from a near-afterthought to one of the hardest problems on the die. Each era added a layer of physics that designers could no longer ignore — and the structure of the grid evolved to match. This is the rough chronology, told through what forced each change.
1960s–70s — power was just wiring
Early SSI/MSI parts — bipolar, then early PMOS and NMOS — had a handful of gates, low currents, and kHz-to-low-MHz clocks. Power was hand-routed alongside the signals on a single aluminum metal layer, often as somewhat wider traces. There was no “grid,” and no IR-drop budget worth analyzing. The only early reliability concern was electromigration in aluminum power lines — Black’s equation (1969) quantified the current-density-versus-lifetime limit, the first time current density in a power conductor became a hard design constraint.
1980s — CMOS, Dennard scaling, and dedicated rails
CMOS took over because it burns power mainly when switching. Dennard scaling (1974) set the rules the industry rode for three decades: shrink dimensions, scale voltage down with them, hold current density roughly constant, and let frequency climb. Two metal layers became normal. The standard-cell methodology fixed the basic structure that still survives — horizontal VDD/VSS rails on the lowest metal, one pair per cell row (the “fishbone”). Power was still simple, but it had become a deliberate, dedicated resource rather than incidental routing.
1990s — the grid proper
This is when the modern power distribution network (PDN) appears. Microprocessors (386 → Pentium) pushed clocks past 100 MHz and power into the tens of watts, and metal stacks grew to four to six layers. Power became a dedicated orthogonal mesh: thick VDD/VSS straps on the upper metal layers, stitched down through via arrays to the cell rails. Several lasting changes land in this decade:
- Static IR-drop analysis becomes a real sign-off step.
- On-chip decoupling capacitance starts being added intentionally (thin-oxide and well capacitors) to source transient current locally.
- Flip-chip / C4 bumps go mainstream for high-performance parts — an area array of power bumps feeding the grid from the top across the whole die, instead of from the periphery through wirebonds. You could now inject power everywhere, not just at the edges.
- Copper interconnect (IBM’s dual-damascene process, announced 1997) replaces aluminum — lower resistance and better electromigration headroom, enabling denser grids.
2000s — the package shows up, and di/dt arrives
GHz clocks and roughly 1 V supplies made the rate of change of current matter. L·di/dt droop became significant, and the field developed the now-standard multi-droop picture: a “first droop” from the on-die decap response, a “second droop” from the package L–C, and a “third droop” from the board and voltage regulator — three impedance peaks at three timescales. Power gating, clock gating, and simultaneous switching introduced sharp di/dt events. Metal stacks reached eight to ten layers with thick top metal for global power, and MIM capacitors appeared in the back end. EDA responded with dynamic voltage-drop tools and vectorless analysis.
The pivotal shift of this decade: the on-die grid could no longer be analyzed in isolation. The package and board had become part of the problem — and this is also when Dennard scaling broke down (around 2004–06): voltage stopped scaling down, power density climbed, and the industry hit the “power wall.”
2010s — FinFETs, power density, and PI-aware design
FinFETs (Intel 22 nm, 2011) gave higher drive current and better leakage control, but power density kept rising. Mobile SoCs made efficiency paramount, bringing many voltage domains, aggressive DVFS, and fine-grained power gating — which means more di/dt transients, not fewer. Power grids became extremely dense and a major consumer of routing resources, which is when power-integrity-aware planning — thinking about the grid early rather than only at sign-off — started to matter. Dynamic droop and grid resonance moved from corner cases to first-order constraints.
2020s — AI currents, backside power, and 3D
AI accelerators broke the trend lines: GPUs and TPUs drawing hundreds of amps and 700 W or more, with current ramps and densities that make voltage droop a dominant design constraint rather than a checkbox. Three structural shifts define the current era:
- Backside power delivery (BSPDN). Moving the power network to the back of the wafer (Intel PowerVia, ~2023–24, with TSMC and Samsung following) decouples power routing from signal routing, slashes IR drop, and frees front-side metal for signals — the biggest change to power-grid topology in decades.
- 2.5D / 3D integration. Chiplets, interposers (CoWoS), HBM stacks, and TSVs mean the PDN now spans board → package → interposer → die → stacked die as one coupled system.
- The grid as an electromagnetic medium. At these di/dt levels and electrical sizes, the on-chip grid has to be treated as a distributed electromagnetic surface — with real propagation, resonance, and field coupling — rather than a resistor mesh.
The arc, at a glance
| Era | What forced the change | The structural answer |
|---|---|---|
| 1960s–70s | Low current, low frequency | Power routed as wider signal traces; electromigration limits emerge |
| 1980s | CMOS + Dennard scaling | Dedicated VDD/VSS cell rails (the fishbone) |
| 1990s | 100+ MHz, tens of watts | Upper-metal orthogonal mesh, IR sign-off, flip-chip feed, on-die decap, copper |
| 2000s | GHz clocks, ~1 V, di/dt | Multi-droop awareness, MIM caps, dynamic-IR tools, package co-analysis |
| 2010s | FinFET power density, mobile | Dense grids, many domains/DVFS, PI-aware planning |
| 2020s | AI-scale current, 3D | Backside power, board-to-die PDN, EM-surface modeling |
The throughline
Each era added a layer of physics that could no longer be ignored: first just resistance and electromigration, then IR drop across a real grid, then package L·di/dt and resonance, and now full board-to-die electromagnetic behavior under AI-scale currents. The structure evolved to match — single traces → cell rails → upper-metal mesh → flip-chip area feed → on-die decap → and now backside delivery and 3D stacks.
That last step — modeling the on-chip grid as a continuum / electromagnetic surface at the planning stage rather than at sign-off — is roughly where Anasim’s PI-FP lineage and PDNLab sit, somewhat ahead of where mainstream on-chip flows have historically operated.