Full-Stack H100 Voltage Droop Analysis in PDNLab™

The semiconductor industry has long understood that dynamically varying voltage droop exists in high-performance processors and has designed circuits and systems to monitor such supply voltage variations. What it has not had is an ability to visualize, pre-silicon, how cumulative voltage droops form and propagate in a large multi-core chip's 3D power delivery network under realistic workloads allocated to the cores. A 158-grid model of the NVIDIA® H100 built in PDNLab™ changes that situation considerably.

The Complexity of Modern AI Silicon

The NVIDIA® H100^[4] is perhaps the most widely deployed AI accelerator in production. The Hopper-architecture GPU contains ~80 billion transistors on an 814 mm² die, fabricated on TSMC's 4N process, consuming up to 700 watts in its SXM5 configuration at a supply voltage of 1.1 V. These are extraordinary numbers. Every characteristic that makes the H100 a powerful AI training engine^[1] also makes it a challenging power delivery and management problem. Supply current levels are extreme, and voltage margins are thin. The switching activity is temporally and spatially complex.

The industry has historically lacked the ability to model what actually happens inside such a chip when block current demand changes rapidly and spatiotemporally^[6]. Full-chip extraction tools that work with the physical design exist, but they are slow, expensive, and generally inaccessible to architects making early-stage decisions about power delivery or power management. The result is that voltage droop analysis has remained a specialized design verification activity, performed late in the design cycle, producing results that are difficult to employ in optimization and nearly impossible to iterate on quickly.

Using published architectural specifications and TSMC process-node data^[2], a full-stack power delivery network model of the H100 was constructed in PDNLab. The model captures the complete path from board-level capacitors through the package substrate and bump array down to all 144 individual Streaming Multiprocessor cores on the die. It contains 158 interconnected grids, 175 current sources, 146 decoupling capacitors, 794 transmission lines, and over 1,500 connection nodes. This model is simulated in minutes in PDNLab rather than hours or days as is typical with 'IR Drop' tools. This article describes how it was built, what assumptions were made, and what the simulation results reveal about the spatiotemporal behavior of voltage droop in modern chips.

Power Delivery Path from Board to Transistors

Power supply energy does not arrive at the transistor in ideal form. It passes through a series of conversion and distribution stages, each with distinct electrical characteristics, each introducing impedance that shapes how voltage responds to transient current demand. Understanding the structure of this path is essential to understanding why droop occurs where and when it does.

The H100's power delivery system spans four physical layers. At the outermost level, the SXM5 carrier board supplies power from more than thirty voltage regulator modules through heavy copper planes. The package substrate, based on TSMC's CoWoS-S technology, routes power from edge-mounted connectors through a multi-layer organic PCB to the silicon. A dense array of approximately five thousand solder bumps connects the package to the die, each with a resistance on the order of 0.15 mΩ. On the die itself, a hierarchical power grid distributes current across the full 28.5 mm × 28.5 mm die area, from thick top-metal global straps down through intermediate layers to the local grids feeding individual computing cores and their transistors.

This layered structure is not unique to the H100. Every modern high-performance processor uses some version of it. What makes the H100 particularly interesting as a modeling subject is the scale. The die size is large, and integrated core count is high. Its power demand is extreme. The result is a power delivery network where the spatial distribution and temporal activation of current demand directly determines the severity and location of voltage droop.

The GH100 die measures approximately 28.5 mm × 28.5 mm. It contains 144 Streaming Multiprocessors organized into 8 Graphics Processing Clusters, along with memory controllers, NVLink engines, and a PCIe block. Given TSMC's 4N process with up to 15 metal layers, the die almost certainly uses a hierarchical power delivery network. The uppermost thick metal layers, likely M14–M15, provide low-resistance global power distribution across the full die area. Intermediate semi-global layers, likely M7–M8, distribute power locally within individual SM core regions. Dense arrays of stacked vias connect these grid levels, with millions of vias in parallel across each SM core area reducing the effective vertical resistance to the sub-micro-Ω range. NVIDIA does not publish exact metal layer assignments, but this two-level hierarchy is consistent with standard practice at advanced nodes.

Constructing the Model

The modeling approach begins where the droop events that matter most actually occur: on the die. The 814 mm² GH100 die is decomposed into functional blocks — SM cores, L2 cache, memory controllers, and NVLink I/O — each represented as a grid element with physically derived electrical parameters. The board and package are represented as lumped impedance feeding into this on-die network. This abstraction is a deliberate choice. Voltage droop events often occur in nanosecond timescales. At those frequencies, the board PDN cannot respond quickly enough to influence the droop waveform because of its electrical distance from the die. A spatially resolved board grid would add computational cost without changing the results. The lumped board representation does not change the accuracy of relevant die-level behavior.

Die-Level Block Decomposition

The first step in constructing the model is dividing the die into functional blocks with estimated area allocations. Using an approximate 60/15/15/10 power budget split as a proxy for area, the 814 mm² die is partitioned as follows:

Functional Block	Area Allocation	Estimated Area	Grid Dimensions in Model
144 SM Cores	~60% (~488 mm²)	~3.39 mm² per SM	1.84 mm × 1.84 mm each
L2 Cache (2 partitions)	~10% (~81 mm²)	~40.5 mm² per partition	1.04 cm × 0.18 cm each
HBM3 Memory Controllers (10)	~15% (~122 mm²)	~12.2 mm² per controller	Distributed along die edges
NVLink + PCIe I/O	~15% (~122 mm²)	Combined I/O block	Grid along bottom edge

Each block in the model is represented as a two-dimensional power grid with its own sheet resistance, inductance, capacitance, and attached current sources. The grid dimensions are derived from the area estimates above. Beyond the 144 SM cores, the model includes dedicated grids for every major functional block: two L2 cache grids flanking the SM array, ten grids along the left and right die edges for first-generation HBM3 memory controller pairs, and a NVLink bus grid along the bottom edge carrying 18 current sources representing the fourth-generation NVLink engine PHYs. This level of functional decomposition ensures that the current distribution across the die reflects the actual H100 architecture, not just the compute cores but the memory subsystem and high-speed I/O that together account for 30 to 40 percent of total power consumption.

Deriving On-Die Capacitance from Transistor Physics

Perhaps the most important parameter for each block is its on-die decoupling capacitance. This is the intrinsic charge storage that resists voltage droop during current transients. In any real processor, this capacitance comes from multiple sources: the gate oxide of transistors themselves, Metal-Insulator-Metal decoupling capacitors integrated within upper metal layers, inter-wire coupling capacitance in the power grid and signal wires, and junction capacitance of transistors.

The derivation begins with TSMC 4N transistor physics. The gate capacitance at this node is approximately 0.18 to 0.22 fF per transistor. With 80 billion transistors across 814 mm², the total intrinsic transistor gate capacitance is approximately 16 µF, yielding a unit capacitance density of roughly 19.66 nF/mm². Incidentally, this device capacitance number yields ~350 W power consumption at a supply voltage of 0.6 V, operating frequency of 690 MHz, and an activity factor of ~0.1 (this used to be 0.05, but since interconnect power consumption equals or exceeds device capacitance contributions, it is doubled in this simplification).

Step	Calculation	Result
Gate capacitance per min-sized transistor	~0.2 fF (midpoint of 0.18–0.22 fF)	0.2 × 10-15 F
Total transistor capacitance	80 × 109 × 0.2 × 10-15 F	~16 µF
Area device capacitance density	16 µF ÷ 814 mm²	~19.66 nF/mm²

This unit density lets us estimate intrinsic capacitance for any block based on its area. However, the model values are intentionally set higher than pure transistor-capacitance calculations, because the on-die power grid includes additional capacitance sources beyond gate oxide. The adjusted values reflect a physically reasonable total that accounts for all contributions:

Block	Area	Calculated C (area × 19.66 nF/mm²)	Model Value (adjusted)	Notes
SM Core (each)	~3.39 mm²	~66.6 nF	110 nF	Adjusted upward for MiM decoupling capacitors in upper metal layers
L2 Cache (each partition)	~40.5 mm²	~796 nF	2 µF	SRAM structures have higher per-area capacitance than logic
HBM3 Memory Controller (each)	~12.2 mm²	~240 nF	300 nF	I/O circuitry with moderate decoupling
NVLink I/O	~122 mm²	~2.4 µF	2.5 µF	High-speed SerDes PHYs with local decoupling

Power Grid Electrical Parameters

Beyond capacitance, each grid element is characterized by wire geometry and electrical properties. The model uses two distinct grid tiers, each derived from published TSMC process-node characteristics for the 5nm/4N family.

The global on-die power distribution network covers the full 28.5 mm × 28.5 mm die area using the uppermost metal layers:

Parameter	Value	Source / Rationale
Grid size	2.85 cm × 2.85 cm	GH100 die dimensions (√814 mm²)
Wire width	3 µm	Wide power straps in top global metal
Wire spacing	15 µm	Power strap pitch for HPC designs
Sheet resistance	0.03 Ω/□	TSMC 4N top global metal (~0.8–1.2 µm thick Cu)
Inductance	3 nH/cm	Closely spaced Vdd/Vss in M14 & M15
Capacitance	2 pF/cm	Global power wire self-capacitance

All 144 Streaming Multiprocessors are modeled as individual grids with their own current sources and decoupling capacitors:

Parameter	Value	Source / Rationale
Grid size	1.84 mm × 1.84 mm	SM core area ≈ 3.39 mm² (488 mm² ÷ 144)
Wire width	1 µm	Semi-global metal routing width
Wire spacing	10 µm	Local power distribution pitch
Sheet resistance	0.3 Ω/□	TSMC 4N semi-global layers (estimated M7–M8)
Inductance	5 nH/cm	Semi-global layer pair
Capacitance	3 pF/cm	Core grid self-capacitance

Current profiles and Cumulative Voltage Droop

A power delivery network model on its own is complex but static. What brings it to life is the varying current demand that flows through it. In PDNLab, every current source is assigned a piece-wise linear waveform specifying current draw as a function of time. The simulator steps through these profiles at each timestep in each simulation resolution area element taking into consideration the change in currents from the previous timepoint. The resulting voltage response across the entire network includes not only the static response (i ·r) but also the dynamic L ·di/dt and the (1/C) ∫i(t) ·dt components.

Generating a current profile requires two pieces of information: the average current a block draws, derived from its power budget and supply voltage, and the temporal shape of switching activity within each clock cycle. The average current sets the total charge per cycle. The shape determines the di/dt — the rate of change of charge draw that drives inductive voltage droop.

The derivation begins with publicly available data. The H100 in its PCIe configuration has a rated TDP (thermal design power) of 350 W. Based on available performance analysis and general GPU architectural trends, a reasonable power budget split allocates approximately 60% of total chip power to the SM cores, with the remainder distributed among I/O, HBM3 memory, and L2 cache. NVIDIA® does not publish exact per-block power, but these assumptions provide a working basis.

Step	Calculation	Result
SM core power budget	60% × 350 W	210 W
Power per SM	210 W ÷ 144 SMs	1.458 W
Average current per SM	1.458 W ÷ 0.6 V (Vdd)	2.43 A

The supply voltage of approximately 0.6 V is consistent with TSMC 4N nominal operating voltage for high-performance transistors. The H100 base clock of approximately 690 MHz gives a clock period of roughly 1.45 ns. At 2.43 A average current, the charge per clock cycle delivered to each SM is approximately 3.52 nC.

Each SM's current profile is constructed as a triangular waveform: two back-to-back triangular pulses per clock cycle, each with a peak of 5 A and a base width of half the clock period. The area under these two triangles in one clock cycle equals the required 3.52 nC of charge. This triangular shape is a preferred representation of time-distributed transistor switching rather than switching limited to clock edges; gate charge and discharge follow smooth RC transitions rather than instantaneous changes, signal evaluations occur between clock edges, and clock skew and jitter spread switching around clock edges. The result is a waveform that draws the correct total charge with much lower di/dt than an equivalent narrow Gaussian profile.

Where available, block current profiles are replaced by actual current consumption waveforms derived from transient simulations. Real current waveforms including leakage, which provides a measure of negative feedback, tend to be less demanding^[3] on the chip PDN, though such effects as voltage-dependency of load current are challenging to incorporate into a passive component modeling and simulation environment. The triangular load current profiles are a reasonable early assumption for qualitative studies of CVD.

The Voltage Margin Problem

Before examining simulation results, it is worth understanding the margins within which the H100 power delivery system must operate. At a nominal V_dd of approximately 0.6 V, the H100 must maintain voltage at switching transistors within tight bounds to ensure correct logic operation. Industry practice typically allows a maximum supply voltage deviation of 5% of V_dd.

Droop Budget	Voltage Drop	Minimum Vdd
5% of Vdd	30 mV	0.570 V
7% of Vdd	42 mV	0.558 V
10% of Vdd	60 mV	0.540 V

A 30 mV droop on a 0.6 V supply is a 5% event. If supply voltage drops below the minimum operating level, logic timing violations can cause silent data corruption or functional failure. The guardband required to absorb this droop directly reduces the maximum achievable clock frequency. For the H100, even small improvements in droop management translate to measurable frequency and throughput gains, or lower power through incremental supply voltage reduction.

But it is not just droop that is a problem; there are often significant voltage overshoots that affect transistor reliability and aging. Resonant circuits swing in both directions, and the sudden turn-OFF of a large switching block, despite soft-switching techniques, can subject transistors to relatively high voltages that degrade their performance over time. This aspect of voltage margin excursion, that could conceivably lead to Silent Data Corruptions over time, is entirely missed by static i ·r drop approximations.

4D Simulation results view on the H100 model

The H100 model uses PDNLab's Scenario Manager to define multiple workload configurations, each assigning different current profiles and activation patterns to current sources across the die. Two scenarios are examined here, while PI analysis and optimization may require many hundreds of them. The first represents "worst-case" synchronous switching. The second represents a more realistic pattern of sequential activation within a local compute cluster.

Full-Synchronous Activation: All 144 SM Cores Firing

The most electrically stressful scenario is often assumed to be full activation: all 144 SM cores drawing current simultaneously with the triangular (or Gaussian) profile described above. Each SM uses a triangular current profile of time period 1.45 ns repeated 3 times, for a total activation window of approximately 4.35 ns. Because every SM draws current in phase, the voltage noise propagating outward from each current source overlaps constructively across the GLOBAL grid, especially near SM cluster centers where the density of active sources is highest and the electrical distance to the nearest bump and lumped capacitor is greatest.

Despite what is thought of as the worst-case synchronous switching scenario, the simulation reveals a peak voltage droop of ~5.9 mV in the GLOBAL power grid (SM-Core-level droop seen in local grids associated with functional blocks is far greater). Constructive interference of simultaneous voltage waves from all 144 SM sources produces a smooth, spatially broad droop envelope rather than a sharp localized spike, because the uniform activation maintains symmetry across the grid and there are no regions demanding more or less charge through the GLOBAL grid impedance.

Staggered Local Activation

The second scenario examines what happens when individual SMs within a single Graphics Processing Cluster fire at slightly offset delays from one another; this scenario attempts to emulate Data Locality ensured by software. SM1 through SM6 and SM8 each use the same triangular current profile, but with artificially staggered start times, and the activation repeats 6 times for an overall simulation window ending at approximately 12 ns. This models the compute wave rippling through the SM pipeline within a GPC, a pattern characteristic of real AI workloads where warp schedulers dispatch work in rapid succession rather than in perfect lockstep.

The result may seem counterintuitive. This staggered activation in a small local cluster produces a larger peak voltage droop of ~7.4 mV in 12 ns of simulation duration in the GLOBAL grid, compared to 5.9 mV in 4.35 ns in the full-synchronous activation case. A reason could be constructive interference of time-staggered voltage waves within a localized region in the larger activation and simulation duration.

This ability to create varied activation scenarios and run Maxwell-accurate simulations in a Full-Stack, true-physical 3D power delivery network is unique to PDNLab™.

Simulations conducted with different intra-SM-Core workload scenarios on a single SM Core show noise on the fractional GLOBAL grid of the SM Core model (seen highlighted at the top of the simulation animation) varying between the two scenarios as below. Voltage droop is many times larger on the fractional grid as compared with the full GLOBAL grid in the H100 model because it is limited in size (and intrinsic capacitance) to the area of the SM Core, isolated with higher impedance, and only connects to a single ideal package/board capacitance.

Voltage droop on any individual SM Core grid (on lower metal layers, M7/M8), in the full-stack H100 simulation, is far more than what is seen on the full GLOBAL grid and correlates with our prior SM Core grid simulations. Similar voltage droop numbers have been measured in NVIDIA® A100 hardware at low loads under resonant excitation^[7]. A single SM Core grid can be seen highlighted above the GLOBAL grid in the simulation animation of localized full-stack H100 activation below. Note that the H100 GLOBAL grid, in our model, is strongly coupled to a large array of ideal capacitors which limits voltage droop in this layer of the 3D model.

The Qualitative Advantage of True PI^[5] Awareness

The value in models and simulations like these is not in specific droop numbers derived, although those do matter. It is in the questions the modeling and simulation environment enables engineers to ask and answer quickly. What happens to the droop envelope if global or SM Core grid wire width are increased or power bus spacing reduced? How much additional MIM capacitance is needed to keep peak cumulative droop within 5% of V_dd? How can we optimize a floorplan for the least noise and, correspondingly, the least supply voltage and power consumption? What is the droop impact of migrating from lateral to vertical (or 'Backside') power delivery? How does the noise distribution change if the SM count is reduced for a lower-power variant? What is the comparative droop behavior of a training workload versus inferential activity? Each of these questions can be answered by modifying model structure, parameters, and scenarios, running simulations, and observing results in tens of minutes rather than hours or days.

We created PDNLab™ with high levels of abstraction and Physics-based simulation capability for this very purpose: to inform designers, early in the physical design flow, of holistic and accurate PI degradation during design, floorplan development, and physical and electrical optimization.

Backside Power Delivery implications to CVD →