Power doesn’t simply “arrive” at an AI accelerator’s transistors. It travels from the board to the gate through a cascade of impedances — voltage regulator, PCB, package, interposer, bumps, through-silicon vias, and the on-die grid — and each layer behaves like a filter that handles one band of transient frequencies. What makes AI hardware different is twofold: the currents are so large and fast they stress every layer at once, and with chiplets, CoWoS interposers, HBM stacks, and 3D stacking, that delivery network is no longer a die on a package — it is one coupled system spanning board → package → interposer → die → stacked die. This is a tier-by-tier breakdown of that stack, and why it has to be analyzed as a whole.
The stack, tier by tier
Follow the charge from the wall to a transistor. Each tier contributes its own resistance, inductance, and capacitance, and each is responsible for a different timescale of the chip’s current demand.
| Tier | What it is | Dominant parasitics | Timescale it serves |
|---|---|---|---|
| VRM / PMIC | Multiphase regulator + control loop on the board | Loop bandwidth, output L | slowest — ~kHz to ~100 kHz |
| Board / PCB | Bulk MLCC banks, power planes, vias | Plane & via L, bulk C | ~100 kHz – ~1 MHz |
| Package substrate | Substrate planes, die-side / land-side caps, silicon caps | Package L + die-side C | ~1 – 10 MHz (“second droop”) |
| Interposer (2.5D) | Si or RDL interposer (CoWoS / EMIB) routing power to several dies | Routing L, TSV L; shared among chiplets + HBM | mid-frequency, shared |
| Bumps / C4 / µ-bumps | Flip-chip area array feeding each die | ~10–50 pH each, thousands in parallel | the gateway into the die |
| TSVs (3D / backside) | Vertical power through stacked dies; backside-power nano-TSVs | TSV L (low) | fast, vertical delivery |
| On-die global grid | Upper thick-metal mesh + on-die decap (MIM / MOS) | Grid L + on-die C | fastest — tens–hundreds of MHz (“first droop”) |
| On-die local grid | M1 VDD/VSS rails into standard cells | Local R dominant | the “last mile” |
| Device | The switching transistors — the load | — | where droop becomes Vmin / timing |
The charge-handoff cascade
The reason the stack is organized by timescale is physical. When a block suddenly demands current, the nearest charge responds first — on-die capacitance, which can deliver in nanoseconds before the inductive grid above it can react. As the demand persists, slower tiers take over the supply in turn: the package, then the board’s bulk capacitors, then finally the VRM’s control loop. Each tier covers the band of frequencies the faster one upstream of it could not.
That hierarchy of L and C produces a hierarchy of resonances — the classic multi-droop picture. Every tier forms an L–C pairing with the one beside it, and each pairing rings at its own natural frequency:
so the impedance the chip sees, looking back into the network, has several peaks — an on-die “first droop” in the tens-to-hundreds of MHz, a package “second droop” around a few MHz, a board/VRM “third droop” far lower. The design goal across the whole stack is a flat target impedance over the band the workload occupies, so that no single frequency gets amplified. As the HPCA 2026 study of LLM–PDN resonance showed, a workload whose power oscillates on one of those peaks can produce far more droop than its raw power swing would imply.
The crux of full-stack analysis. The most dangerous resonances do not live inside any one tier — they live between tiers. Package inductance ringing against on-die capacitance is a peak that neither the package nor the die shows on its own. Analyze the layers in isolation and you miss exactly the failures that matter.
2.5D and 3D integration: the stack becomes one coupled system
For decades the stack ended at “a die on a package.” AI hardware broke that. Reticle limits, yield, and cost pushed designs away from one giant monolithic die toward disaggregated chiplets mounted together — and that change reaches all the way down into power delivery. The PDN now genuinely spans board → package → interposer → die → stacked die, with every die electrically coupled to its neighbors through shared structure.
- Chiplets on an interposer (CoWoS / EMIB). Multiple compute dies sit on a shared silicon interposer or bridge that routes both signals and power between them. Because they draw from a common interposer and package PDN, a transient on one chiplet develops a voltage across the shared inductance that every other chiplet sees. One die’s workload can erode its quiet neighbor’s margin — so a chiplet cannot be signed off in isolation.
- HBM stacks sharing the PDN. High-bandwidth memory is itself a 3D stack — eight to twelve DRAM dies over a logic base die, bonded with TSVs — and it sits on the same interposer as the logic. HBM refresh and burst currents inject noise into the logic supply through the shared package/interposer inductance. The memory and the compute are not on independent power networks; they are coupled.
- TSVs and vertical delivery. In a 3D stack, power reaches the upper dies vertically through through-silicon vias and micro-bumps between tiers. A die buried in the middle of a stack is electrically far from the package feed, and its droop depends on the impedance of the entire column above and below it — a buried-die penalty that only a full-stack model reveals.
- Backside power delivery (BSPDN). The newest shift moves the power network to the back of the wafer, fed by nano-TSVs, decoupling power routing from signal routing on the front. It reshapes the on-die portion of the stack entirely — lowering IR drop and freeing front-side metal — but it adds yet another vertical tier whose interaction with the rest of the network has to be modeled, not assumed.
The common thread: integration has turned a chain of mostly-independent tiers into a single, laterally and vertically coupled network. Disturbances no longer just travel up and down the stack — they travel sideways, chiplet to chiplet and memory to logic, through shared interposer and package structure.
Why it has to be modeled as one system
Two facts make tier-by-tier sign-off insufficient for AI hardware. First, as above, the worst resonances are inter-tier — they exist only when the package, interposer, bumps, and die are solved together. Second, the dangerous coupling is now inter-die — chiplet-to-chiplet and HBM-to-logic interactions that simply do not appear when each die is analyzed alone. A model that stops at the die boundary, or that lumps the whole system to a single node, cannot answer where on which die a buried droop concentrates, or how a neighbor’s burst arrives.
This is the case for full-system, board-to-die modeling — the principle behind Anasim’s PI-FP and PDNLab. The board, package, interposer, bumps, and TSVs are represented as transmission lines; the on-die grids as continuum electromagnetic surfaces; and the whole assembly is solved as one coupled network, with a large reservoir capacitance standing in for an ideal source at the system boundary. Because complexity in the continuum method scales with the physics rather than the polygon count, it remains tractable even at the scale a real accelerator demands — a full PDNLab model of an H100-class part spans on the order of a hundred-plus interconnected grids, hundreds of transmission lines, and thousands of connection nodes, board through die.
The full-stack PDN of AI hardware is no longer a sequence of layers you can clear one at a time. It is a coupled board-to-die system, and the failures that matter — inter-tier resonance, chiplet crosstalk, HBM-to-logic noise, buried-die droop — live in the coupling. Seeing them means modeling the whole stack at once.