“Power integrity” sounds like one task, but no single EDA tool does it. It is a pipeline, and each commercial tool owns one stage: one estimates the current, another extracts the parasitics, another solves the on-die grid for voltage drop, another analyzes the package impedance. To understand what these tools actually do — and, just as importantly, where their methods stop — it helps to walk the pipeline stage by stage and name the tools at each.
The pipeline, in six stages
Whatever the vendor, a modern power-integrity flow is some version of this sequence:
- 1. Estimate the current — RTL/gate power and switching activity produce the load.
- 2. Extract the parasitics — the resistance and capacitance of the die, and the RLCG of the package and board.
- 3. Solve the on-die network — static IR drop, then dynamic IR drop.
- 4. Check reliability — electromigration and current density.
- 5. Analyze the package/board PDN — frequency-domain impedance, resonance, decoupling.
- 6. Close timing and temperature — voltage-aware timing and electrothermal coupling.
Stage 1 — estimating the current
Everything downstream is only as good as the current it is given. These tools compute power and switching activity, either vectorless (statistically, from activity factors) or vector-based (from a real simulation trace), and emit the per-block current the analysis tools consume.
RTL is only the structure of the design — the Verilog tells the tool what logic exists, but nothing about how often it switches or what each gate costs in energy. To turn that into current, a power tool needs several other inputs supplied alongside the RTL:
- Switching activity — the single most important addition, and exactly what separates “vector-based” from “vectorless”:
- Vector-based: you run a logic simulation of a real workload or testbench and capture the toggling — as a VCD (value-change dump), the faster FSDB, or a condensed SAIF (switching-activity interchange format, which stores per-net toggle rates and static probabilities). These dumps are “the vectors.”
- Vectorless: no simulation — the tool propagates statistical activity factors and default toggle rates inward from the clocks and primary inputs. Faster and available earlier, but not faithful to any specific workload.
- Characterized cell libraries — the Liberty (.lib) models for every standard cell and macro, giving per-cell internal, switching, and leakage power, usually with CCS-Power / ECSM current models for accurate waveforms, across process-voltage-temperature corners. Without these the tool has no idea what a gate costs.
- Power intent — a UPF (or CPF) file describing power domains, power switches, isolation, and retention. Essential for anything with power gating or multiple supply voltages.
- Timing constraints — an SDC file defining the clocks and their frequencies, so the tool knows how fast things actually switch.
- For gate-level accuracy — the synthesized netlist plus extracted SPEF parasitics, since wire capacitance drives a large share of switching power.
- Operating conditions — the supply voltage, temperature, and process corner to evaluate at.
What the tool produces is not a single wattage but a per-instance, per-block power and current profile over time — the current “signature” the downstream IR tools place geographically on the die. The accuracy ladder runs from RTL plus statistical activity (rough, available on day one), to RTL plus SAIF (better), to a gate netlist with SPEF and an FSDB from a real workload (accurate, slow, and only available late). And the whole result is only as representative as the workload that was simulated: unrepresentative vectors mean every droop number downstream inherits the error.
| Tool | Vendor | What it does |
|---|---|---|
| PowerArtist | Ansys | RTL power estimation & reduction; activity and power scenarios |
| PrimePower | Synopsys | Gate/RTL dynamic + leakage power; scenario generation |
| Joule | Cadence | RTL / system-level power |
| PowerPro | Siemens EDA | RTL power estimation & reduction |
Stage 2 — extraction and field solvers
These turn physical geometry into electrical elements. On-die, that means RC extraction; for the package and board, it means quasi-static or full-wave electromagnetic solvers that produce R, L, C, and G.
The inputs are the physical layout — DEF/LEF during implementation, or final GDSII/OASIS — together with a description of the process stack: an ITF / techfile / nxtgrd giving each metal layer’s thickness and resistivity and the dielectric constants between layers. On-die, the extractor walks that geometry and emits a SPEF (or DSPF) listing the resistance and capacitance of every net. For the package and board, a field solver takes the package layout (ODB++, Allegro .brd, or GDS for an interposer), the layer stackup, and material properties, has the user define ports (where current enters and leaves), and solves Maxwell’s equations to emit an S-parameter model (Touchstone .sNp) or a broadband SPICE subcircuit capturing R, L, C, and G. Quasi-static extraction (Q3D) is fast; full-wave (HFSS, Clarity) stays accurate to higher frequencies.
| Tool | Vendor | What it does |
|---|---|---|
| StarRC / Quantus | Synopsys / Cadence | On-die RC parasitic extraction |
| Q3D | Ansys | Quasi-static RLCG extraction of package/board interconnect |
| HFSS | Ansys | Full-wave 3D finite-element EM solver — the high-frequency gold standard |
| SIwave | Ansys | Planar/hybrid solver for PCB & package planes: PDN impedance, plane resonance |
| Clarity 3D Solver | Cadence | Full-wave 3D EM solver |
Stage 3 — on-die PI sign-off (the core)
This is what most engineers mean by “PI tools.” They take the extracted grid and the per-cell currents and solve for the voltage drop across the die. Concretely, they do four things:
- Static IR drop — a DC solve of the resistive grid using average currents, finding steady hotspots:
- Dynamic IR drop — a transient solve of the (predominantly RC) network with time-varying cell current sources. Two modes:
- Vectorless — statistically constructs a worst-case switching scenario from activity, no simulation required.
- Vector-based — driven by a real workload trace (VCD/FSDB).
- Electromigration (EM) — wire current density checked against lifetime limits.
- Power — total and peak power, per instance.
To run any of this, the tool wires together four things: the extracted power-grid network (the RC — sometimes RLC — of the on-die PDN, from Stage 2); the per-instance current from Stage 1, placed at real physical coordinates via the DEF; cell current models (CCS-Power / ECSM) so each cell’s draw over time is known; and a boundary model of the package and board — the S-parameter or SPICE PDN from Stage 4 — attached at the bump / C4 map, alongside the on-die decap. Static IR is then a DC matrix solve; dynamic IR is a transient solve of that network with the time-varying current sources, either over a tool-synthesized worst-case window (vectorless) or a real FSDB trace (vector-based). The outputs are voltage-drop maps, EM violations, and IR-derated timing.
| Tool | Vendor | What it is |
|---|---|---|
| RedHawk-SC | Ansys | Cloud-native on-die static/dynamic IR, EM, power — the incumbent sign-off |
| Voltus | Cadence | On-die PI sign-off (static/dynamic IR, EM, power), tied to the Innovus flow |
| mPower | Siemens EDA | Digital + analog PI / reliability (IR, EM, power), full-chip |
| PrimeRail | Synopsys | Rail / IR & EM sign-off in the PrimeTime / Fusion flow; voltage-aware timing |
| Totem · Voltus-XFi | Ansys · Cadence | Transistor-level PI for custom / analog / mixed-signal blocks |
Stage 4 — the package and board PDN
This is where impedance and resonance are genuinely handled — but for the package and board, in the frequency domain. These tools compute the PDN impedance Z(f), find its peaks and anti-resonances, target a flat impedance across the band, and optimize decoupling capacitance.
The inputs are the package and board layout and stackup, material properties, a set of port definitions (typically a die-side port and the VRM port), and a decap library holding the discrete capacitors’ own models. The solver returns the impedance Z(f) looking into the network, the frequencies of its peaks, and an S-parameter model that is handed up to the on-die analysis in Stage 3 as its boundary condition — which is how the two halves of the flow connect.
| Tool | Vendor | What it does |
|---|---|---|
| Sigrity — PowerSI | Cadence | Frequency-domain PDN impedance and plane coupling |
| Sigrity — PowerDC | Cadence | DC IR drop + thermal for package/board |
| Sigrity — OptimizePI | Cadence | Decoupling-capacitor placement optimization |
| SIwave / HFSS | Ansys | Package/board PDN impedance, resonance, return paths |
| HyperLynx | Siemens EDA | Board/package SI/PI, decoupling, plane impedance |
| ADS / PathWave | Keysight | RF, board, and system-level power integrity |
Stage 5 — SPICE, the golden reference
Transistor-level transient simulation is the most accurate option and the ultimate reference — but it does not scale to a full chip, so it is used on critical nets and to calibrate the faster tools.
SPICE needs the transistor-level netlist, the foundry device models (BSIM model cards), the extracted parasitics for the nets in question, and a stimulus. It then integrates the circuit equations directly in time — the most faithful answer available, and the reference against which the faster, more abstracted tools are calibrated.
| Tool | Vendor | What it does |
|---|---|---|
| HSPICE · PrimeSim · FineSim | Synopsys | Circuit-level transient simulation |
| Spectre · Spectre X | Cadence | Circuit-level transient simulation |
| Analog FastSPICE (AFS) | Siemens EDA | Accelerated transistor-level simulation |
Stage 6 — electrothermal and reliability
Power raises temperature, temperature raises resistance, and reliability rules constrain the grid. A final tier of tools closes those loops.
The inputs here are the power map from Stages 1 and 3, a thermal model (material conductivities, the package’s thermal resistance, the heatsink boundary), and the layout. The tool solves for the temperature distribution, updates conductor resistances accordingly, and re-runs the IR solve — because hotter metal is more resistive, the electrical and thermal problems are genuinely coupled rather than separable.
| Tool | Vendor | What it does |
|---|---|---|
| RedHawk-SC Electrothermal | Ansys | Couples power → temperature → resistance |
| Celsius | Cadence | Electrothermal co-simulation |
| Calibre PERC | Siemens EDA | Electrical rule checks: point-to-point resistance, current density, EM/ESD robustness |
Stitching the on-die, package, and board tiers together is the job of chip-package-system (CPS) co-analysis flows, which pass models between these tools.
The recurring pattern. Every stage needs four ingredients: the design (RTL or layout), a model of the technology (Liberty, ITF, device models), a representation of the workload (SAIF / VCD / FSDB, or a statistical stand-in), and a boundary model handed over from the neighboring stage. The hand-offs between tools quite literally are those file formats — SAIF, SPEF, S-parameters — and the accuracy of the whole flow is set by the weakest link in that chain.
What they do well
It is worth being fair about how capable this toolchain is. Collectively it delivers mature, accurate static and dynamic IR at full-chip scale, integrated into sign-off; excellent frequency-domain package/board PDN impedance and resonance analysis; real electromigration and electrothermal checking; and, with cloud-native platforms, the elasticity to run on the largest dies. The division of labor across the pipeline works, and for decades of conventional processor design it served the industry well.
Where the methodology stops
The limits are not about any one tool failing — they are about where the mainstream methodology is centered. Five gaps matter:
- On-die inductance is largely omitted. The dominant on-die sign-off tools are resistive / lumped-RC at heart. They capture I·R and RC dynamic droop, but on-die L·di/dt and wave/propagation effects — the components growing fastest at advanced nodes — are underrepresented.
- A split brain. On-die tools are spatial but not inductive: they resolve where, in RC. Package/board tools are inductive and frequency-domain but not spatially on-die: they see resonance, but collapse the die to terminals. No mainstream tool delivers on-die, spatial, inductive, transient analysis in one place — that quadrant is empty.
- They run late. These are sign-off tools; they need a finished or near-finished netlist, after place-and-route. The highest-leverage power decisions — floorplan, grid topology, decap strategy — are made before these tools can run.
- Full-chip transient is expensive. A field-solver extraction of every on-die segment yields hundreds of millions of nodes; solving that transiently at nanosecond resolution across microseconds of workload is days-to-weeks per scenario, which makes design-space exploration impractical.
- Vectorless is not a workload. Statistical worst-case construction can miss workload-specific phenomena — for instance a power oscillation that aligns with a PDN resonance — that only appear with the right temporal current profile.
The shape of the gap. On-die tools see space but not inductance; package tools see inductance but not on-die space; and all of them run after the design is largely frozen. The missing capability is a fast, true-electromagnetic, on-die and inductive analysis that can run at the planning stage, on abstract data, and unify the spatial and inductive views the rest of the toolchain splits apart.
The opening
That missing quadrant is the reason a different class of approach exists — one built around a continuum, true-electromagnetic formulation rather than node-by-node lumped extraction, so it captures on-die inductance and propagation, scales with the physics instead of the polygon count, and runs early enough to inform floorplanning. This is the line Anasim’s PI-FP engine and PDNLab pursue: not a replacement for IR-drop sign-off, but a complement that fills the part of the picture the established methodology was never designed to show. Understanding what today’s tools do — and precisely where they stop — is the first step to knowing what still needs to be added.
Vendor capabilities evolve quickly and overlap; tool names and feature sets here reflect the broad market roles as of writing, and several vendors are actively adding inductance-aware and earlier-stage analysis. The gaps described are where the mainstream methodology centers, not absolute statements about any single product.