The Cerebras Wafer-Scale Engine is the largest chip ever built — an entire silicon wafer, roughly 21.5 cm on a side, operated as one monolithic processor. It also draws about 25 kilowatts into that single piece of silicon, at a supply of about a volt, which works out to on the order of 25,000 amperes. At that scale, the way every other chip gets its power simply does not work. The WSE is where power delivery stops being a packaging detail and becomes the binding constraint — and where the physics forces a particular set of answers.

The chip, for scale

The WSE-3 is fabricated on TSMC’s N5 process as a single monolithic wafer — a 12 × 7 grid of 84 identical reticle dies, stitched together across the scribe lines into one chip of about 46,225 mm². It carries around 900,000 enabled cores (out of ~970,000, the spare ones harvested for yield) and roughly half its area is SRAM — about 44 GB at ~21 PB/s. For comparison, a large GPU die is on the order of 800 mm². The wafer is something like fifty times that area, in one connected piece.

A large GPU die ~800 mm² ~2.8 cm The Cerebras WSE 46,225 mm² · ~21.5 cm · 84 stitched dies ≈ 50× the area
One WSE is a whole wafer — about fifty large GPU dies’ worth of silicon (the highlighted cell is one of its 84 reticle dies), operated as a single connected chip.

Why wafer scale breaks normal power delivery

A conventional chip is one to three centimeters across, and it is fed power through an area array of bumps from the package below. You can tolerate the voltage drop of moving current those short distances. A wafer cannot. Two facts make ordinary delivery impossible:

  • Lateral IR drop is fatal. Pushing ~25,000 A sideways across 21.5 cm of on-die metal to reach the center would drop the supply far past any usable budget long before it arrived. There is no metal stack thick enough. Power simply cannot enter from the edge.
  • The grid is electrically enormous. Across a die that large, the “everything is at one voltage” assumption fails completely. Disturbances propagate with real delay; the on-wafer power network is a genuine two-dimensional distributed R–L–C medium with ~900,000 switching cores embedded in it.

So the power has to arrive a different way: not from the rim, but from above — perpendicular to the wafer, distributed across its entire face, so that no region is ever far from a feed.

Edge delivery — fails at wafer scale deep droop edge: full V power enters only at the rim Vertical area delivery — the WSE way fed from above, everywhere → uniform V
Fed from the edge, the center of a wafer starves (red = deep droop). The only workable answer is to feed power vertically, from above, across the whole face — every region gets its own local supply.

The solution: power delivered vertically, brick per die

Cerebras delivers power through the third dimension, in a voltage hierarchy that steps down as it gets closer to the silicon. Publicly reported figures describe it roughly as follows:

  • 12 power supplies at 50 V feed twelve stacked power-distribution boards.
  • Those boards carry 84 Vicor power bricks — one per reticle die — converting 50 V → 12 V.
  • A final stage at the silicon converts 12 V → ~1 V, delivered perpendicular to the wafer.

The structure mirrors the chip itself: one power brick per die, feeding straight down into its block, so the 25,000 amperes enter as 84 local streams spread uniformly across the face rather than one impossible river from the edge.

25 kW ÷ ~1 V ≈ 25,000 A  ·  delivered as 84 vertical feeds

The engine block, and the CTE problem

Holding all of this together is a four-layer sandwich Cerebras calls the engine block: a cold plate, the wafer, a compliant connector, and the power board. The hard part is not the layers — it is that they don’t expand the same way.

Silicon and the PCB beneath it have different coefficients of thermal expansion, and across a 21.5 × 21.5 cm span, the difference as everything heats up is large enough to crack a conventional rigid package. The fix is compliance built into two interfaces: a compliant connector between the wafer and the power board that carries current while flexing to absorb the differential motion, and a cold-plate face that is polished and held against the wafer under preload so the two can slide relative to each other while staying in thermal contact. That connector is not just mechanical — it is part of the power path, in the current the wafer draws, so its resistance and inductance are part of the PDN.

The “engine block” Cold plate (water) WSE wafer (silicon) Compliant connector Power board (PCB) connector flexes to absorb CTE mismatch Voltage hierarchy 12 × PSU 50 V input 84 Vicor bricks (1 / die) 50 V → 12 V at the die 12 V → ~1 V ≈ 25,000 A into the wafer at 1 V
The engine block sandwiches the wafer between a sliding cold plate and a compliant connector that carries power while absorbing the silicon-vs-PCB expansion mismatch. Power steps down 50 V → 12 V → 1 V, one brick per die.

What it means for power integrity

Strip away the system engineering and the WSE is a power-integrity problem taken to its absolute limit — and it makes several principles unavoidable that, on smaller chips, a designer can sometimes get away with ignoring:

  • IR drop is survivable only because delivery is vertical and uniform. The design rule “every region needs its own local feed” is not a guideline here; it is the only thing that keeps the center of the wafer alive.
  • The grid is a true electromagnetic surface. With ~900,000 cores switching across 21.5 cm, transient disturbances propagate as waves with measurable delay; the L·di/dt and resonance physics that smaller dies can sometimes treat as lumped become genuinely distributed.
  • Decoupling has to live everywhere. Local charge reservoirs must blanket the wafer, because upstream charge is far in time even when it is near in space.
  • Node-by-node modeling is hopeless. A wafer-scale grid is billions of nodes; enumerating and solving it transiently is intractable. Only a method whose cost scales with the physics rather than the polygon count — a continuum formulation — can analyze a power network this large at all.

The deeper point. The WSE is the clearest existence proof that the continuum, electromagnetic-surface view of the on-chip power grid is not academic. At wafer scale it is simply the only view that works — and the answers it forces (uniform vertical area delivery, local decoupling everywhere, the grid solved as one distributed medium) are exactly the planning-stage, full-stack philosophy of true-physical power-integrity analysis, pushed to the edge of what silicon allows.

A preview, not a curiosity

It is tempting to file wafer-scale power delivery under “exotic.” But the direction of the whole industry — reticle-stitched system-on-wafer designs, ever-larger multi-die packages, vertical power delivery, backside power, hundreds of amperes climbing toward thousands — is pointed straight at the regime the WSE already lives in. Cerebras simply got there first, because it had no choice. The lesson it teaches about power — deliver it everywhere, vertically; decouple it locally; and model the grid as the distributed electromagnetic medium it actually is — is the lesson the rest of high-performance silicon is steadily learning too.

Architecture, power, and packaging figures (25 kW; 50 V → 12 V → 1 V; 12 supplies / 84 Vicor bricks; the four-layer engine block and CTE-compliant connector; 84 dies / ~900k cores / 44 GB SRAM) are as publicly reported, including in SemiAnalysis’s Cerebras analysis. The power-integrity discussion here is first-principles; Cerebras has not published on-wafer droop or PDN data, and no specific droop figures are claimed.