A chip is full of capacitors — some deliberately placed, many simply unavoidable. They rarely get the attention transistors do, but they do something just as essential: they are the chip’s local reservoir of charge, and they are what holds the supply voltage up in the instant millions of transistors switch at once. Here is what these on-chip capacitors are, where they come from, and the physical story of how they deliver charge to the transistors.
What a capacitor is, on a chip
A capacitor is just two conductors separated by a thin insulator (a dielectric). Charge it up and it holds a reservoir of charge proportional to the voltage across it, storing energy in the electric field between the plates:
On a chip, a capacitor of this kind sits between the power network (Vdd) and the ground network (Vss). Charged to the supply voltage, it becomes a tiny, local battery of charge — ready to release current the moment the circuit nearby asks for it. Add up all of these across the die and you get the chip’s on-die capacitance, often quoted as a capacitance per unit area (for example, a few µF/cm²).
Two kinds: the ones you get, and the ones you add
On-die capacitance comes from two sources. A surprising amount of it is simply there for free; the rest is engineered in on purpose.
| Capacitance | What it is | Intentional? |
|---|---|---|
| Intrinsic gate / junction | The gate capacitance of every transistor not currently switching, plus well and junction capacitances — quietly sitting between the rails. | No — inherent |
| Grid / wire | The capacitance between the power and ground metal of the distribution grid itself. | No — inherent |
| MOS-cap (decap cell) | A transistor deliberately wired as a capacitor (gate against channel), dropped into empty floorplan area as a standard cell. | Yes |
| MIM capacitor | A metal–insulator–metal capacitor built up in the back-end metal stack. | Yes |
| Deep-trench capacitor | A capacitor etched vertically into the silicon for very high density per area. | Yes |
The intentional ones are collectively called decoupling capacitance, or “decap.” The whole purpose of adding them is to put stored charge as close as possible to the circuits that will suddenly need it.
Why a chip needs them: the charge problem
Consider what happens when a single logic gate switches — say its output flips from 0 to 1. To do that, it must charge its output node up to Vdd, which means pulling a packet of charge off the supply rail:
and it must do so in picoseconds, the gate’s switching time. One gate is nothing. But an AI accelerator switches millions of them in near-synchrony on every clock edge, so the chip demands an enormous packet of charge almost instantaneously. The question that decides whether the supply survives is simple: where does that charge come from in the first nanoseconds?
It cannot come from the package and board fast enough. The grid feeding power from the bumps upward has inductance, and inductance resists fast changes in current — the familiar L·di/dt effect. If the inductive grid were the only source, the local voltage would collapse before the charge could arrive from upstream.
How they deliver charge
This is exactly the gap on-die capacitance fills. A capacitor sitting right next to the switching circuit, connected through a very short, low-inductance path, can release its stored charge almost instantly — far faster than the inductive grid above it can respond. When the transistors demand current, electrons flow off the capacitor’s plates, through the local connection, into the switching circuit. The capacitor’s stored energy (½CV²) is handed over as that current.
The result is a relay race for charge, organized by speed:
- First nanoseconds: the nearby on-die capacitor supplies the fast transient.
- Then: as that capacitor drains, slower reservoirs refill it in turn — the package capacitors, the board’s bulk capacitors, and finally the voltage regulator — each covering the band of demand the faster one upstream could not.
The role in one line. On-die capacitance is a charge buffer between the slow upstream delivery network and the fast downstream demand. It effectively shorts out the grid’s inductance for fast events by handing over charge that is already local.
The cost of delivering: a small voltage sag
Releasing charge is not free. As charge leaves the capacitor, its own voltage drops:
That sag is part of the supply’s voltage droop — but it is far shallower than the collapse the bare inductive grid would have produced. A larger local capacitance means a smaller sag for the same charge drawn, which is why “is there enough capacitance near this block?” is usually the first question in any droop investigation. If a region of the chip is short on its share of capacitance, it will show artificially deep droop that no amount of grid widening can fix.
Placement beats quantity
There is one subtlety that separates effective decap from wasted decap: a capacitor only delivers fast charge if the inductance of the loop connecting it to the load is low — that is, if it is physically close. The same number of farads parked far away, out at the package, cannot dump charge quickly, because the inductance between it and the load slows the delivery. This is why on-die capacitance handles the fast, high-frequency demand while package and board capacitance handle only the slower demand — and why, when deciding where decap goes, placement matters as much as the amount.
It is also why more is not always better. Because capacitance pairs with the grid and package inductance, adding it carelessly can shift a resonance into the band a workload actually excites — so on-die capacitance is a precise instrument, not a quantity to be maximized. (We go deeper on tuning it, and on the rest of the design knobs, in Modeling with PDNLab.)
Part of a larger reservoir
Zoom out and the on-die capacitors are the fastest tier of a much larger system of reservoirs — on-die for the picosecond-to-nanosecond demands, package capacitors for the microsecond range, board bulk capacitors slower still, and the regulator slowest of all. Each is a stage in the same charge-handoff cascade that delivers power from the wall to the gate, which we trace tier by tier in The Full-Stack PDN of AI Hardware.
The capacitors inside a chip are easy to overlook, but they are doing continuous, invisible work: every clock edge, they catch the surge of demand the rest of the network is too slow to meet, and hold the supply steady long enough for the charge behind them to arrive.