Simultaneous Switching in AI Compute: The Systolic Array and the Global Power Grid

The systolic array is the dominant compute structure in AI silicon because it maximizes arithmetic per unit of memory traffic. The same regularity that makes it efficient also makes it a coherent, clock-synchronous electrical load: thousands of identical processing elements switching in lockstep. This article breaks down how a systolic array computes, why its switching is simultaneous rather than statistically averaged, and how that coherent current draw loads the global power grid — a regime conventional, distributed-logic power analysis does not anticipate.

How a systolic array computes

A systolic array is a grid of identical processing elements (PEs), each connected only to its nearest neighbors. Every PE performs one multiply-accumulate per clock cycle, and data is pumped through the array one PE per cycle — the rhythmic dataflow from which the name derives (Kung and Leiserson, 1978).

For a matrix multiply, the weights are held resident in the PEs, the activations stream in from one edge of the array, and partial sums accumulate as they advance and exit the opposite edge. Each operand is read from memory once and reused across an entire row or column of PEs. That data reuse is the entire point: it converts a memory-bandwidth-bound operation into a compute-bound one, with minimal control overhead. A Google TPU matrix unit is a 128×128 array — 16,384 multiply-accumulate units operating in parallel; GPU tensor cores and dedicated NPUs are built on the same principle.

From computation to current

Electrically, each PE is a multiply-accumulate datapath that draws a current pulse when it switches on the clock edge. An array is thousands of these datapaths, and during a dense matrix-multiply burst essentially all of them are active on every cycle. The array's aggregate current is therefore the sum of many identical, time-aligned current pulses.

The magnitudes are concrete. On an H100 streaming multiprocessor at a 0.6 V core rail and a 690 MHz clock (a 1.45 ns period), a warpgroup matrix-multiply burst draws on the order of 4 A concentrated in roughly 18% of the SM area, against a per-SM average near 2.43 A. The charge pulled from the local power-delivery network each cycle is approximately Q = I · t ≈ 2.43 A × 1.45 ns ≈ 3.5 nC. Across a full device of 130-plus such SMs, the aggregate is thousands of amperes — delivered, and withdrawn, in step with the clock.

Why the switching is simultaneous

Simultaneous switching is the coherent, time-aligned switching of many identical elements. It is the defining electrical characteristic of a systolic array, and it is the opposite of what conventional power analysis assumes.

In general-purpose logic, switching is data-dependent and skewed in time across the clock period. Activity is statistically decorrelated, currents partially cancel, and the aggregate draw is comparatively smooth and low in di/dt. Vectorless and statistical IR-drop methods depend on exactly this averaging.

A systolic array removes that diversity by construction. The PEs are identical, clocked together, and active together throughout a burst, so their multiply-accumulate current spikes align to the clock edge and superpose constructively. The result is a large, sharp aggregate current step on every cycle — high di/dt, with no statistical cancellation. This is the worst-case stimulus a power grid can receive, and the architecture generates it deliberately and continuously.

How the coherent load reaches the grid

The power-delivery network must source the array's charge demand within each cycle, across a frequency hierarchy: on-die decoupling capacitance supplies the highest-frequency component, the on-die grid and package supply the mid-frequency, and the voltage regulator supplies the DC. A coherent current step ΔI with edge time Δt develops a voltage of L · (ΔI / Δt) across the inductance of the grid and package, in addition to the I · R drop across its resistance. At the di/dt of a synchronized array, the inductive term dominates — and it is invisible to static IR-drop analysis, which models only resistance.

Because a systolic array occupies a large, contiguous die area, its current is drawn across that whole area and must be delivered from the C4 bumps through the upper-metal global grid and the package — not solely through local metal. The array's coherent load is therefore a load on the global power grid, and the global grid's inductance, not just local IR, sets the depth of the resulting droop.

The global grid as a propagation medium

The global grid is a distributed resistance-inductance-capacitance structure, so a coherent current step does not appear everywhere at once. It launches a voltage disturbance that propagates across the grid as a wave at finite velocity; on a large die, corner-to-corner propagation is 10 to 50 ns. Simultaneous switching across the array drives the grid at its fundamental spatial mode — the mode most prone to large-amplitude oscillation.

The dataflow imposes spatial structure on top of this. As activations stream through the array, the active region — and the droop trough that tracks it — sweeps across the die in the direction of dataflow. The array's edges and the bump array act as reflection boundaries, and disturbances launched by adjacent arrays or cores can converge and add. The aggregate result is a moving, structured voltage field across the global grid, not a uniform offset.

Resonance under periodic excitation

A single burst is a transient; a sustained matrix multiply is a periodic coherent load. The clock and the burst cadence place energy at frequencies that coincide with the global PDN's resonances — approximately 50 to 500 MHz at the die-to-package interface and 1 to 50 MHz at the package-to-board interface. At those frequencies the network impedance peaks, and the droop produced by a coherent current step is amplified rather than damped. The familiar mid-frequency "first droop" on a load step becomes a repeated, potentially reinforced event when the array switches on the same schedule cycle after cycle.

Why this requires full-stack, dynamic modeling

None of this is captured by static IR-drop or by a lumped PDN model. Static analysis omits the inductive L·di/dt term entirely; a lumped model omits propagation, the spatial structure of the load, and the resonances of the distributed grid. The simultaneous-switching behavior of a systolic array is, by definition, a distributed and dynamic phenomenon, and it must be analyzed as one.

That requires driving a distributed model of the full grid — board, package, and die — with the array's actual coherent, time-resolved current, and observing the spatiotemporal voltage response. This is the analysis PDNLab performs: per-block current sources that each carry an explicit (x, y) coordinate, attached to a continuum representation of the grid, so that the array's synchronized current can be played against the physical global network and the resulting droop surface read directly. The methodology for constructing such a model is documented in our walkthrough of an AI accelerator core, and the broader case for per-workload analysis in why AI cores must be modeled with PDNLab.

The efficiency of the systolic array and its electrical hazard are the same property. The regularity that lets it convert memory traffic into dense arithmetic is the regularity that makes its switching coherent, simultaneous, and inductively severe on the global grid. The architecture that delivers the FLOPS delivers the worst-case load to the power network — and only a full-stack, dynamic analysis of the two together can establish whether the supply holds.