“2.5D” and “3D” cover a dozen distinct technologies, and the brand names — CoWoS, EMIB, Foveros, SoIC, HBM — get used loosely. This is a direct breakdown: what each one is, how it connects dies, and where it is used. No build-up.
Why it exists
Monolithic scaling hit three walls: the reticle limit (~858 mm² is the largest a single die can be), yield (one defect can kill a huge die), and cost. The response is to split a design into smaller chiplets and reconnect them with advanced packaging. The three regimes differ by how the dies are connected.
| Regime | How dies connect | Density / bandwidth |
|---|---|---|
| 2D | Side by side, through the package substrate | Coarse, low |
| 2.5D | Side by side, on a fine-pitch interposer or bridge | Fine, high (lateral) |
| 3D | Stacked vertically, through the silicon (TSVs / bonding) | Highest, shortest path |
Most AI chips use 2.5D and 3D at the same time.
2.5D — lateral integration
In 2.5D, dies sit beside each other on a high-density layer instead of the coarse substrate. There are three approaches.
Silicon interposer (TSMC CoWoS). A large slab of silicon with fine routing and through-silicon vias. Chiplets and HBM stacks sit on top of it; it sits on the package substrate. CoWoS = “Chip-on-Wafer-on-Substrate.” Three variants:
| Variant | Interposer | Trade-off |
|---|---|---|
| CoWoS-S | Full passive silicon interposer | Highest density; expensive; reticle-size-limited |
| CoWoS-R | Organic / RDL interposer | Cheaper, coarser, more flexible in size |
| CoWoS-L | RDL with embedded local silicon bridges | Bridge-grade density only where dies meet; reaches large, reticle-stitched areas |
Embedded bridge (Intel EMIB). Instead of a full interposer, a small silicon bridge is buried inside the organic substrate, giving dense connections only where two chiplets meet. Cheaper than an interposer, scales to large packages, uses no large piece of silicon. Used in Sapphire Rapids; combined with 3D in Ponte Vecchio.
Fan-out (TSMC InFO). “Integrated Fan-Out.” Routing is built directly around the die in redistribution layers, with no silicon interposer at all. InFO_PoP (package-on-package) is used in Apple mobile SoCs; InFO_oS targets larger parts. Lower cost and lower density than a silicon interposer.
Equivalents from other vendors: Samsung I-Cube (silicon interposer), Amkor S-Connect, ASE FOCoS.
The vertical building blocks
Three components make stacking possible. They are not packages themselves — they are how vertical connections are formed.
| Component | What it is | Pitch |
|---|---|---|
| TSV | Through-silicon via — a copper via through a thinned die, front to back. Enables both interposers and stacking. | — |
| C4 bump | Die-to-package/interposer solder bump. | ~100–150 µm |
| Micro-bump | Die-to-die solder bump for 2.5D/3D. | tens of µm |
| Hybrid bonding (Cu-Cu) | Direct copper-to-copper + dielectric bonding — no solder. The leading edge. | sub-10 µm → sub-1 µm |
Hybrid bonding is the key recent shift: dropping from microbump pitch to sub-micron raises connection density by roughly an order of magnitude and cuts the parasitic resistance and inductance of each link.
3D — vertical stacking
In 3D, dies are stacked and connected through the silicon. The named technologies are mostly hybrid-bonding flows.
| Technology | Vendor | What it is |
|---|---|---|
| Foveros | Intel | Face-to-face 3D logic stacking via microbumps. Used in Meteor Lake, Ponte Vecchio. |
| Foveros Direct | Intel | Foveros upgraded to hybrid bonding. |
| SoIC | TSMC | Hybrid-bonding 3D stacking. Used for AMD’s 3D V-Cache. |
| X-Cube / SAINT | Samsung | Samsung’s 3D hybrid-bonding stack. |
| 3D V-Cache | AMD (on TSMC SoIC) | Stacks an extra SRAM cache die directly on top of the CPU core die. |
The trade-off is fixed: 3D gives the shortest interconnect and the highest bandwidth, at the cost of a hard thermal problem — a buried die cannot shed heat easily.
HBM — the main use of 3D today
High Bandwidth Memory is itself a 3D stack: 4-, 8-, 12-, or 16-high DRAM dies over a logic base die, bonded with TSVs and microbumps (HBM4 is moving to hybrid bonding and customizable base dies). Each stack exposes a 1024-bit-wide interface for very high bandwidth, and it sits on the 2.5D interposer next to the compute die.
This is why a single AI “chip” uses both regimes: a compute chiplet (sometimes itself 3D-stacked) plus several HBM stacks (each 3D), all mounted on a CoWoS-class interposer (2.5D).
The connective tissue
UCIe (Universal Chiplet Interconnect Express). The 2022 industry standard for die-to-die communication — a common physical and protocol layer so chiplets from different vendors can interoperate across these packages. It turns advanced packaging into an open chiplet ecosystem.
Wafer-scale integration (Cerebras WSE). The opposite extreme: rather than disaggregating, use an entire wafer as one chip via reticle stitching. A different answer to the same reticle limit.
Why it matters for power
Every one of these reshapes power delivery. TSVs and hybrid bonds become vertical power paths. The interposer and bridges create a power network shared among chiplets and HBM, so one die’s transient couples into another. A buried 3D die sits electrically far from the package feed. The practical consequence: the power delivery network of a modern part is a single coupled system spanning board to stacked die, not a chip on a package — the subject of The Full-Stack PDN of AI Hardware.