Original analysis of the power-integrity challenges shaping AI silicon, chip architecture, and data-center economics.
A real on-chip power grid is a dozen-layer mess. PI-FP reduces it to an equivalent two-layer symmetric transmission-line grid — and the symmetry is what makes it solvable. Why the horizontal current in the global grid carries the dominant noise, with diagrams.
Read articleBetween the silicon die and the board sit two layers that determine how a chip is powered, connected, and held together. A direct breakdown of the package substrate and the interposer — what each is, what it is made of, where it sits in the stack, and why AI parts need both.
Read articleAn LLM’s computation is almost entirely matrix multiplication. A precise breakdown of what actually enters the compute units — activations and weights, their shapes and precision — and how a transformer layer decomposes into the matmuls the matrix engine runs across training, prefill, and decode.
Read articleA grid of identical processing elements through which data is pumped one step per clock cycle, each performing a single multiply-accumulate. How it computes a matrix multiply and why it is so efficient — the matrix engine at the heart of AI silicon, explained with diagrams.
Read articleA systolic array is thousands of identical processing elements switching in lockstep. That coherent, clock-synchronous current is the worst-case stimulus for a power grid — an inductive, distributed, resonant load on the global PDN that static IR-drop analysis cannot see.
Read articleAn AI core's droop surface is its physical power grid convolved with a specific workload's spatiotemporal current — so there is no single droop to sign off. How workload patterns and the physical layout each sculpt the droop surface, and why every workload deserves its own model.
Read articleEvery LLM inference request is really two computations with opposite hardware appetites — prefill reads the prompt and is compute-bound; decode writes the answer and is memory-bound. The split, as Cerebras frames it, explains modern inference hardware — and the two distinct power-delivery signatures it draws at the rail.
Read articleModern AI accelerators drive current transients so fast the power delivery network can no longer be treated as a simple RC circuit. Why L·di/dt droop — not IR drop — is now a fundamental determinant of whether an AI chip computes correctly.
Read articleWhat you can actually tune in a power-grid model — wire width, pitch, sheet resistance, inductance, and capacitance — what each one physically does, and why damping turns the grid into an R–L–C system rather than a resistor.
Read articleAt the switching speeds of modern AI silicon, the grid stops acting like wiring and starts acting like a continuous electromagnetic medium — storing energy in fields, carrying disturbances as waves, and coupling every conductor to its neighbors. A first-principles explanation.
Read articleHow on-chip power distribution evolved from a routing afterthought into one of the hardest problems on the die — from single aluminum traces to upper-metal meshes, flip-chip feed, on-die decap, and backside power delivery.
Read articleA recap of Raj Nair’s 2008 EE Times argument: behind the Power Wall sits a Power Integrity Wall, with inductive L·di/dt noise doubling every process generation. The Roots-of-Two derivation — and why AI silicon walked straight into it.
Read articleA walkthrough of Jiang et al. (HPCA 2026, UT Austin & AMD): how LLM inference excites GPU PDN resonance, their ladder RLC model, the result where a 10 W swing at resonance beats a 100 W swing off it, and a warp-staggering fix.
Read articlePower travels from board to transistor through a cascade of impedances — VRM, PCB, package, interposer, bumps, TSVs, on-die grid. With chiplets, CoWoS, HBM stacks, and 3D, that PDN is now one coupled system spanning board to stacked die. A tier-by-tier breakdown.
Read articleEvery chip is full of capacitors — some added, some unavoidable. They are the chip’s local charge reservoir: what holds the supply voltage up the instant millions of transistors switch. What on-die capacitance is, the types, and how it delivers charge.
Read articleInside a modern chip program: the team, the lifecycle, and the experienced power-delivery engineer who dictates how current reaches every transistor — and who asks, early, the questions that decide whether a superchip’s power holds.
Read articlePower integrity isn’t one tool — it’s a pipeline, and each commercial EDA tool owns one stage. A breakdown vendor by vendor and method by method: RTL power, extraction, on-die IR sign-off, package PDN impedance, SPICE, electrothermal — and where the methodology stops.
Read articleA direct breakdown of modern advanced packaging: the 2D / 2.5D / 3D taxonomy and each technology — CoWoS, EMIB, InFO, TSVs, microbumps, hybrid bonding, Foveros, SoIC, HBM, and UCIe — what it is, how it connects dies, and who uses it.
Read articleHow a die connects to its package — and the key to keeping it straight: which way the active face points. A clear, diagram-led explanation of face-up vs face-down, the C4 bump, and why the industry flipped the chip over.
Read articleThe WSE draws ~25 kW into one 21.5 cm silicon square — about 25,000 A at 1 V. At that scale edge delivery is impossible. How power is fed vertically across the whole wafer, the CTE-mismatch connector, and why wafer scale forces the continuum view of power integrity.
Read articleFor modern AI chips the limiter is rarely compute — it’s memory. Why moving data, not doing math, sets the pace: the bandwidth-vs-capacity trade-off, bandwidth-bound decode, the KV cache, the SRAM scaling cliff, HBM and DRAM — and why it’s an energy problem too.
Read article